220 lines
8.1 KiB
Verilog
220 lines
8.1 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_snp_forwarder #(
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parameter CACHE_ID = 0,
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parameter SRC_ADDR_WIDTH = 1,
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parameter DST_ADDR_WIDTH = 1,
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parameter NUM_REQS = 1,
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parameter SREQ_SIZE = 1,
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parameter TAG_IN_WIDTH = 1,
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parameter TAG_OUT_WIDTH = `LOG2UP(SREQ_SIZE)
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) (
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input wire clk,
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input wire reset,
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// Snoop request
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input wire snp_req_valid,
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input wire [SRC_ADDR_WIDTH-1:0] snp_req_addr,
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input wire snp_req_inv,
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input wire [TAG_IN_WIDTH-1:0] snp_req_tag,
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output wire snp_req_ready,
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// Snoop response
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output wire snp_rsp_valid,
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output wire [SRC_ADDR_WIDTH-1:0] snp_rsp_addr,
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output wire snp_rsp_inv,
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output wire [TAG_IN_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready,
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// Snoop Forwarding out
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output wire [NUM_REQS-1:0] snp_fwdout_valid,
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output wire [NUM_REQS-1:0][DST_ADDR_WIDTH-1:0] snp_fwdout_addr,
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output wire [NUM_REQS-1:0] snp_fwdout_inv,
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output wire [NUM_REQS-1:0][TAG_OUT_WIDTH-1:0] snp_fwdout_tag,
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input wire [NUM_REQS-1:0] snp_fwdout_ready,
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// Snoop forwarding in
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input wire [NUM_REQS-1:0] snp_fwdin_valid,
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input wire [NUM_REQS-1:0][TAG_OUT_WIDTH-1:0] snp_fwdin_tag,
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output wire [NUM_REQS-1:0] snp_fwdin_ready
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);
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localparam ADDR_DIFF = DST_ADDR_WIDTH - SRC_ADDR_WIDTH;
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localparam NUM_REQUESTS_QUAL = NUM_REQS * (1 << ADDR_DIFF);
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localparam REQ_QUAL_BITS = `LOG2UP(NUM_REQUESTS_QUAL);
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if (NUM_REQS > 1) begin
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reg [REQ_QUAL_BITS:0] pending_cntrs [SREQ_SIZE-1:0];
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wire [TAG_OUT_WIDTH-1:0] sfq_write_addr, sfq_read_addr;
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wire sfq_full;
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wire [TAG_OUT_WIDTH-1:0] fwdin_tag;
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wire fwdin_valid;
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wire fwdin_ready = snp_rsp_ready || (1 != pending_cntrs[sfq_read_addr]);
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wire fwdin_fire = fwdin_valid && fwdin_ready;
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assign snp_rsp_valid = fwdin_valid && (1 == pending_cntrs[sfq_read_addr]);
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assign sfq_read_addr = fwdin_tag;
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wire sfq_acquire = snp_req_valid && snp_req_ready;
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wire sfq_release = snp_rsp_valid && snp_rsp_ready;
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VX_cam_buffer #(
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.DATAW (SRC_ADDR_WIDTH + 1 + TAG_IN_WIDTH),
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.SIZE (SREQ_SIZE)
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) req_metadata_buf (
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.clk (clk),
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.reset (reset),
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.write_addr (sfq_write_addr),
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.acquire_slot (sfq_acquire),
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.read_addr (sfq_read_addr),
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.write_data ({snp_req_addr, snp_req_inv, snp_req_tag}),
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.read_data ({snp_rsp_addr, snp_rsp_inv, snp_rsp_tag}),
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.release_addr (sfq_read_addr),
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.release_slot (sfq_release),
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.full (sfq_full)
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);
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wire fwdout_valid;
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wire [TAG_OUT_WIDTH-1:0] fwdout_tag;
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wire [DST_ADDR_WIDTH-1:0] fwdout_addr;
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wire fwdout_inv;
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wire fwdout_ready;
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wire dispatch_hold;
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if (ADDR_DIFF != 0) begin
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reg [TAG_OUT_WIDTH-1:0] fwdout_tag_r;
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reg [DST_ADDR_WIDTH-1:0] fwdout_addr_r;
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reg fwdout_inv_r;
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reg dispatch_hold_r;
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always @(posedge clk) begin
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if (reset) begin
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dispatch_hold_r <= 0;
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end else begin
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if (snp_req_valid && snp_req_ready) begin
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dispatch_hold_r <= 1;
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end
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if (dispatch_hold_r
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&& fwdout_ready
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&& (fwdout_addr[ADDR_DIFF-1:0] == ((1 << ADDR_DIFF)-1))) begin
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dispatch_hold_r <= 0;
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end
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end
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if (fwdout_valid && fwdout_ready) begin
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fwdout_addr_r <= fwdout_addr + DST_ADDR_WIDTH'(1'b1);
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end
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if (snp_req_valid && snp_req_ready) begin
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fwdout_inv_r <= snp_req_inv;
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fwdout_tag_r <= sfq_write_addr;
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end
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end
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assign fwdout_valid = dispatch_hold_r || (snp_req_valid && !sfq_full);
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assign fwdout_tag = dispatch_hold_r ? fwdout_tag_r : sfq_write_addr;
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assign fwdout_addr = dispatch_hold_r ? fwdout_addr_r : {snp_req_addr, ADDR_DIFF'(0)};
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assign fwdout_inv = dispatch_hold_r ? fwdout_inv_r : snp_req_inv;
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assign dispatch_hold= dispatch_hold_r;
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end else begin
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assign fwdout_valid = snp_req_valid && !sfq_full;
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assign fwdout_tag = sfq_write_addr;
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assign fwdout_addr = snp_req_addr;
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assign fwdout_inv = snp_req_inv;
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assign dispatch_hold= 1'b0;
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end
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always @(posedge clk) begin
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if (sfq_acquire) begin
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pending_cntrs[sfq_write_addr] <= NUM_REQUESTS_QUAL;
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end
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if (fwdin_fire) begin
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pending_cntrs[sfq_read_addr] <= pending_cntrs[sfq_read_addr] - 1;
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end
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end
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reg [NUM_REQS-1:0] snp_fwdout_ready_other;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign snp_fwdout_valid[i] = fwdout_valid && snp_fwdout_ready_other[i];
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assign snp_fwdout_addr[i] = fwdout_addr;
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assign snp_fwdout_inv[i] = fwdout_inv;
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assign snp_fwdout_tag[i] = fwdout_tag;
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end
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always @(*) begin
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snp_fwdout_ready_other = {NUM_REQS{1'b1}};
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for (integer i = 0; i < NUM_REQS; i++) begin
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for (integer j = 0; j < NUM_REQS; j++) begin
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if (i != j)
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snp_fwdout_ready_other[i] &= snp_fwdout_ready[j];
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end
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end
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end
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assign fwdout_ready = (& snp_fwdout_ready);
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assign snp_req_ready = fwdout_ready && !sfq_full && !dispatch_hold;
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VX_stream_arbiter #(
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.NUM_REQS (NUM_REQS),
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.DATAW (TAG_OUT_WIDTH),
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.IN_BUFFER (NUM_REQS >= 4),
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.OUT_BUFFER (NUM_REQS >= 4)
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) snp_fwdin_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (snp_fwdin_valid),
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.data_in (snp_fwdin_tag),
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.ready_in (snp_fwdin_ready),
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.valid_out (fwdin_valid),
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.data_out (fwdin_tag),
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.ready_out (fwdin_ready)
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);
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`ifdef DBG_PRINT_CACHE_SNP
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always @(posedge clk) begin
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if (fwdin_valid && fwdin_ready) begin
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$display("%t: cache%0d snp-fwd-in: tag=%0h", $time, CACHE_ID, fwdin_tag);
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end
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end
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`endif
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign snp_fwdout_valid = snp_req_valid;
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assign snp_fwdout_addr = snp_req_addr;
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assign snp_fwdout_inv = snp_req_inv;
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assign snp_fwdout_tag = snp_req_tag;
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assign snp_req_ready = snp_fwdout_ready;
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assign snp_rsp_valid = snp_fwdin_valid;
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assign snp_rsp_addr = snp_req_addr;
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assign snp_rsp_inv = snp_req_inv;
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assign snp_rsp_tag = snp_fwdin_tag;
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assign snp_fwdin_ready = snp_rsp_ready;
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end
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`ifdef DBG_PRINT_CACHE_SNP
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always @(posedge clk) begin
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if (snp_req_valid && snp_req_ready) begin
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$display("%t: cache%0d snp-fwd-req: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, `TO_FULL_ADDR(snp_req_addr), snp_req_inv, snp_req_tag);
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end
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if (snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin
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$display("%t: cache%0d snp-fwd-out: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, `TO_FULL_ADDR(snp_fwdout_addr[0]), snp_fwdout_inv[0], snp_fwdout_tag[0]);
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end
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if (snp_rsp_valid && snp_rsp_ready) begin
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$display("%t: cache%0d snp-fwd-rsp: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, snp_rsp_addr, snp_rsp_inv, snp_rsp_tag);
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end
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end
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`endif
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endmodule |