136 lines
5.0 KiB
Verilog
136 lines
5.0 KiB
Verilog
`include "VX_define.vh"
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module VX_commit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_commit_if alu_commit_if,
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VX_commit_if ld_commit_if,
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VX_commit_if st_commit_if,
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VX_commit_if csr_commit_if,
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`ifdef EXT_F_ENABLE
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VX_commit_if fpu_commit_if,
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`endif
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VX_commit_if gpu_commit_if,
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// outputs
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VX_writeback_if writeback_if,
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VX_cmt_to_csr_if cmt_to_csr_if
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);
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localparam CMTW = $clog2(3*`NUM_THREADS+1);
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// CSRs update
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wire alu_commit_fire = alu_commit_if.valid && alu_commit_if.ready;
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wire ld_commit_fire = ld_commit_if.valid && ld_commit_if.ready;
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wire st_commit_fire = st_commit_if.valid && st_commit_if.ready;
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wire csr_commit_fire = csr_commit_if.valid && csr_commit_if.ready;
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`ifdef EXT_F_ENABLE
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wire fpu_commit_fire = fpu_commit_if.valid && fpu_commit_if.ready;
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`endif
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wire gpu_commit_fire = gpu_commit_if.valid && gpu_commit_if.ready;
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wire commit_fire = alu_commit_fire
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|| ld_commit_fire
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|| st_commit_fire
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|| csr_commit_fire
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`ifdef EXT_F_ENABLE
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|| fpu_commit_fire
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`endif
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|| gpu_commit_fire;
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wire [`NUM_THREADS-1:0] commit_tmask1, commit_tmask2, commit_tmask3;
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assign commit_tmask1 = alu_commit_fire ? alu_commit_if.tmask:
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ld_commit_fire ? ld_commit_if.tmask:
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csr_commit_fire ? csr_commit_if.tmask:
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`ifdef EXT_F_ENABLE
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fpu_commit_fire ? fpu_commit_if.tmask:
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`endif
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0;
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assign commit_tmask2 = st_commit_fire ? st_commit_if.tmask : 0;
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assign commit_tmask3 = gpu_commit_fire ? gpu_commit_if.tmask : 0;
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wire [CMTW-1:0] commit_size;
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assign commit_size = $countones({commit_tmask3, commit_tmask2, commit_tmask1});
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VX_pipe_register #(
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.DATAW (1 + CMTW),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.data_in ({commit_fire, commit_size}),
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.data_out ({cmt_to_csr_if.valid, cmt_to_csr_if.commit_size})
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);
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// Writeback
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VX_writeback #(
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.CORE_ID(CORE_ID)
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) writeback (
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.clk (clk),
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.reset (reset),
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.alu_commit_if (alu_commit_if),
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.ld_commit_if (ld_commit_if),
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.csr_commit_if (csr_commit_if),
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`ifdef EXT_F_ENABLE
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.fpu_commit_if (fpu_commit_if),
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`endif
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.writeback_if (writeback_if)
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);
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// store and gpu commits don't writeback
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assign st_commit_if.ready = 1'b1;
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assign gpu_commit_if.ready = 1'b1;
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (alu_commit_if.valid && alu_commit_if.ready) begin
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$write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.wb, alu_commit_if.rd);
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`PRINT_ARRAY1D(alu_commit_if.data, `NUM_THREADS);
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$write("\n");
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end
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if (ld_commit_if.valid && ld_commit_if.ready) begin
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$write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, ld_commit_if.wid, ld_commit_if.PC, ld_commit_if.tmask, ld_commit_if.wb, ld_commit_if.rd);
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`PRINT_ARRAY1D(ld_commit_if.data, `NUM_THREADS);
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$write("\n");
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end
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if (st_commit_if.valid && st_commit_if.ready) begin
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$display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d", $time, CORE_ID, st_commit_if.wid, st_commit_if.PC, st_commit_if.tmask, st_commit_if.wb, st_commit_if.rd);
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end
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if (csr_commit_if.valid && csr_commit_if.ready) begin
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$write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=CSR, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.wb, csr_commit_if.rd);
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`PRINT_ARRAY1D(csr_commit_if.data, `NUM_THREADS);
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$write("\n");
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end
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`ifdef EXT_F_ENABLE
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if (fpu_commit_if.valid && fpu_commit_if.ready) begin
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$write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.wb, fpu_commit_if.rd);
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`PRINT_ARRAY1D(fpu_commit_if.data, `NUM_THREADS);
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$write("\n");
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end
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`endif
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if (gpu_commit_if.valid && gpu_commit_if.ready) begin
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$write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=GPU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.wb, gpu_commit_if.rd);
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`PRINT_ARRAY1D(gpu_commit_if.data, `NUM_THREADS);
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$write("\n");
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end
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end
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`endif
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endmodule
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