faf5fe3838
Since the core's response ready signal depends on response valid, but core does not accept write ACKs, we need to manually assert ready when there is a valid response coming in for a write regardless of the core's ready state (which would be 0).
584 lines
22 KiB
Systemverilog
584 lines
22 KiB
Systemverilog
`include "VX_define.vh"
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`include "VX_gpu_pkg.sv"
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// TODO: move VX_define constants to parameters, and then parameterize in blackbox
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module Vortex import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0,
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parameter BOOTROM_HANG100 = 32'h10100,
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parameter NUM_THREADS = 0
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) (
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/* adapt to CoreIO bundle at src/main/scala/tile/Core.scala */
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input clock,
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input reset,
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// input hartid,
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input [31:0] reset_vector,
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input interrupts_debug,
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input interrupts_mtip,
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input interrupts_msip,
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input interrupts_meip,
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input interrupts_seip,
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input imem_0_a_ready,
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input imem_0_d_valid,
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input [2:0] imem_0_d_bits_opcode,
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// input [1:0] imem_0_d_bits_param,
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input [3:0] imem_0_d_bits_size,
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input [ICACHE_TAG_WIDTH-1:0] imem_0_d_bits_source,
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// input [2:0] imem_0_d_bits_sink,
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// input imem_0_d_bits_denied,
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input [31:0] imem_0_d_bits_data,
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// input imem_0_d_bits_corrupt,
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output imem_0_a_valid,
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output [2:0] imem_0_a_bits_opcode,
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// output [2:0] imem_0_a_bits_param,
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output [3:0] imem_0_a_bits_size,
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output [ICACHE_TAG_WIDTH-1:0] imem_0_a_bits_source,
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output [31:0] imem_0_a_bits_address,
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output [3:0] imem_0_a_bits_mask,
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output [31:0] imem_0_a_bits_data,
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// output imem_0_a_bits_corrupt,
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output imem_0_d_ready,
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input dmem_0_a_ready,
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input dmem_0_d_valid,
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input [2:0] dmem_0_d_bits_opcode,
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// input [1:0] dmem_0_d_bits_param,
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input [3:0] dmem_0_d_bits_size,
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input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_0_d_bits_source,
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// input [2:0] dmem_0_d_bits_sink,
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// input dmem_0_d_bits_denied,
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input [31:0] dmem_0_d_bits_data,
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// input dmem_0_d_bits_corrupt,
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output dmem_0_a_valid,
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output [2:0] dmem_0_a_bits_opcode,
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// output [2:0] dmem_0_a_bits_param,
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output [3:0] dmem_0_a_bits_size,
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output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_0_a_bits_source,
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output [31:0] dmem_0_a_bits_address,
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output [3:0] dmem_0_a_bits_mask,
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output [31:0] dmem_0_a_bits_data,
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// output dmem_0_a_bits_corrupt,
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output dmem_0_d_ready,
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input dmem_1_a_ready,
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input dmem_1_d_valid,
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input [2:0] dmem_1_d_bits_opcode,
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// input [1:0] dmem_1_d_bits_param,
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input [3:0] dmem_1_d_bits_size,
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input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_1_d_bits_source,
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// input [2:0] dmem_1_d_bits_sink,
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// input dmem_1_d_bits_denied,
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input [31:0] dmem_1_d_bits_data,
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// input dmem_1_d_bits_corrupt,
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output dmem_1_a_valid,
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output [2:0] dmem_1_a_bits_opcode,
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// output [2:0] dmem_1_a_bits_param,
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output [3:0] dmem_1_a_bits_size,
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output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_1_a_bits_source,
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output [31:0] dmem_1_a_bits_address,
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output [3:0] dmem_1_a_bits_mask,
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output [31:0] dmem_1_a_bits_data,
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// output dmem_1_a_bits_corrupt,
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output dmem_1_d_ready,
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input dmem_2_a_ready,
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input dmem_2_d_valid,
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input [2:0] dmem_2_d_bits_opcode,
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// input [1:0] dmem_2_d_bits_param,
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input [3:0] dmem_2_d_bits_size,
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input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_2_d_bits_source,
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// input [2:0] dmem_2_d_bits_sink,
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// input dmem_2_d_bits_denied,
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input [31:0] dmem_2_d_bits_data,
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// input dmem_2_d_bits_corrupt,
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output dmem_2_a_valid,
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output [2:0] dmem_2_a_bits_opcode,
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// output [2:0] dmem_2_a_bits_param,
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output [3:0] dmem_2_a_bits_size,
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output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_2_a_bits_source,
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output [31:0] dmem_2_a_bits_address,
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output [3:0] dmem_2_a_bits_mask,
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output [31:0] dmem_2_a_bits_data,
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// output dmem_2_a_bits_corrupt,
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output dmem_2_d_ready,
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input dmem_3_a_ready,
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input dmem_3_d_valid,
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input [2:0] dmem_3_d_bits_opcode,
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// input [1:0] dmem_3_d_bits_param,
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input [3:0] dmem_3_d_bits_size,
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input [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_3_d_bits_source,
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// input [2:0] dmem_3_d_bits_sink,
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// input dmem_3_d_bits_denied,
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input [31:0] dmem_3_d_bits_data,
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// input dmem_3_d_bits_corrupt,
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output dmem_3_a_valid,
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output [2:0] dmem_3_a_bits_opcode,
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// output [2:0] dmem_3_a_bits_param,
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output [3:0] dmem_3_a_bits_size,
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output [DCACHE_NOSM_TAG_WIDTH-1:0] dmem_3_a_bits_source,
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output [31:0] dmem_3_a_bits_address,
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output [3:0] dmem_3_a_bits_mask,
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output [31:0] dmem_3_a_bits_data,
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// output dmem_3_a_bits_corrupt,
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output dmem_3_d_ready,
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// input fpu_fcsr_flags_valid,
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// input [4:0] fpu_fcsr_flags_bits,
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// // input [63:0] fpu_store_data,
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// input [31:0] fpu_toint_data,
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// input fpu_fcsr_rdy,
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// input fpu_nack_mem,
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// input fpu_illegal_rm,
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// input fpu_dec_wen,
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// input fpu_dec_ldst,
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// input fpu_dec_ren1,
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// input fpu_dec_ren2,
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// input fpu_dec_ren3,
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// input fpu_dec_swap12,
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// input fpu_dec_swap23,
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// input [1:0] fpu_dec_typeTagIn,
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// input [1:0] fpu_dec_typeTagOut,
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// input fpu_dec_fromint,
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// input fpu_dec_toint,
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// input fpu_dec_fastpipe,
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// input fpu_dec_fma,
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// input fpu_dec_div,
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// input fpu_dec_sqrt,
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// input fpu_dec_wflags,
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// input fpu_sboard_set,
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// input fpu_sboard_clr,
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// input [4:0] fpu_sboard_clra,
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// output fpu_hartid,
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// output [31:0] fpu_time,
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// output [31:0] fpu_inst,
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// output [31:0] fpu_fromint_data,
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// output [2:0] fpu_fcsr_rm,
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// output fpu_dmem_resp_val,
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// output [2:0] fpu_dmem_resp_type,
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// output [4:0] fpu_dmem_resp_tag,
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// output fpu_valid,
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// output fpu_killx,
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// output fpu_killm,
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// output fpu_keep_clock_enabled,
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output cease,
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input traceStall,
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output wfi
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);
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logic [3:0] intr_counter;
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logic msip_1d, intr_reset;
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logic busy;
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assign intr_reset = |intr_counter;
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/* interrupts */
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always @(posedge clock) begin
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msip_1d <= interrupts_msip;
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if (reset) begin
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intr_counter <= 4'h0;
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end else if (~msip_1d && interrupts_msip) begin
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// rising edge
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intr_counter <= 4'h6;
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end else begin
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intr_counter <= intr_counter > 0 ? intr_counter - 4'h1 : 4'h0;
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end
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end
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// ------------------------------------------------------------------------
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// TL <-> Vortex core-cache interface adapter
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// ------------------------------------------------------------------------
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VX_mem_bus_if #(
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.DATA_SIZE (ICACHE_WORD_SIZE),
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.TAG_WIDTH (ICACHE_TAG_WIDTH)
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) icache_bus_if();
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// NOTE(hansung): need to use DCACHE_NOSM_TAG_WIDTH here instead of
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// DCACHE_TAG_WIDTH; the latter is only used inside the core to
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// differentiate between requests going to the outside cache vs. going to
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// the shared memory.
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_WORD_SIZE),
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.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
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) dcache_bus_if[DCACHE_NUM_REQS]();
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// always @(posedge clock) begin
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// `ASSERT(DCACHE_NUM_REQS == NUM_THREADS, "DCACHE_NUM_REQS doesn't match NUM_THREADS");
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// end
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/* imem */
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assign icache_bus_if.rsp_valid = imem_0_d_valid;
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// TODO: hardcoded DCACHE_WORD_SIZE = 4
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assign icache_bus_if.rsp_data.data = imem_0_d_bits_data;
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assign icache_bus_if.rsp_data.tag = imem_0_d_bits_source[ICACHE_TAG_WIDTH-1:0];
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assign imem_0_d_ready = icache_bus_if.rsp_ready;
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// always @(posedge clock) begin
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// if (icache_req_if.valid && icache_req_if.ready)
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// icache_rsp_if.tag <= icache_req_if.tag;
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// end
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assign imem_0_a_bits_source = {32'b0, icache_bus_if.req_data.tag}[ICACHE_TAG_WIDTH-1:0];
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assign imem_0_a_valid = icache_bus_if.req_valid;
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assign imem_0_a_bits_address = {icache_bus_if.req_data.addr, 2'b0};
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assign icache_bus_if.req_ready = imem_0_a_ready;
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assign imem_0_a_bits_data = 32'd0;
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assign imem_0_a_bits_mask = 4'hf;
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// assign imem_0_a_bits_corrupt = 1'b0;
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// assign imem_0_a_bits_param = 3'd0;
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assign imem_0_a_bits_size = 4'd2; // 32b
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assign imem_0_a_bits_opcode = 3'd4; // Get
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/* dmem */
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// Vortex core does not accept write acks; filter them out here
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assign dcache_bus_if[0].rsp_valid =
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(dmem_0_d_valid && (dmem_0_d_bits_opcode !== 3'd0 /*AccessAck*/));
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assign dcache_bus_if[1].rsp_valid =
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(dmem_1_d_valid && (dmem_1_d_bits_opcode !== 3'd0 /*AccessAck*/));
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assign dcache_bus_if[2].rsp_valid =
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(dmem_2_d_valid && (dmem_2_d_bits_opcode !== 3'd0 /*AccessAck*/));
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assign dcache_bus_if[3].rsp_valid =
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(dmem_3_d_valid && (dmem_3_d_bits_opcode !== 3'd0 /*AccessAck*/));
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assign dcache_bus_if[0].rsp_data.data = dmem_0_d_bits_data;
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assign dcache_bus_if[1].rsp_data.data = dmem_1_d_bits_data;
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assign dcache_bus_if[2].rsp_data.data = dmem_2_d_bits_data;
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assign dcache_bus_if[3].rsp_data.data = dmem_3_d_bits_data;
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// get tag (source) from one of the valid dmem lanes; any is fine, use
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// priority logic for simplicity
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// logic [9:0] tag_d;
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// always @(*) begin
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// tag_d = '0;
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// for (integer i = 0; i < 4; i += 1) begin
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// if ({dmem_3_d_valid, dmem_2_d_valid, dmem_1_d_valid, dmem_0_d_valid}[i]) begin
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// tag_d = {dmem_3_d_bits_source, dmem_2_d_bits_source, dmem_1_d_bits_source, dmem_0_d_bits_source}[i * 10 +: 10];
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// end
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// end
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// end
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// assign dcache_rsp_if.tag = tag_d;
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assign dcache_bus_if[0].rsp_data.tag = dmem_0_d_bits_source;
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assign dcache_bus_if[1].rsp_data.tag = dmem_1_d_bits_source;
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assign dcache_bus_if[2].rsp_data.tag = dmem_2_d_bits_source;
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assign dcache_bus_if[3].rsp_data.tag = dmem_3_d_bits_source;
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// When there's a write ACK coming back, ready bit should always be 1 to
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// accept them because core does not accept them on their own
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assign dmem_0_d_ready = dcache_bus_if[0].rsp_ready || (dmem_0_d_bits_opcode == 3'd0 /*AccessAck*/);
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assign dmem_1_d_ready = dcache_bus_if[1].rsp_ready || (dmem_1_d_bits_opcode == 3'd0 /*AccessAck*/);
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assign dmem_2_d_ready = dcache_bus_if[2].rsp_ready || (dmem_2_d_bits_opcode == 3'd0 /*AccessAck*/);
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assign dmem_3_d_ready = dcache_bus_if[3].rsp_ready || (dmem_3_d_bits_opcode == 3'd0 /*AccessAck*/);
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assign dmem_0_a_valid = dcache_bus_if[0].req_valid;
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assign dmem_1_a_valid = dcache_bus_if[1].req_valid;
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assign dmem_2_a_valid = dcache_bus_if[2].req_valid;
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assign dmem_3_a_valid = dcache_bus_if[3].req_valid;
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assign dmem_0_a_bits_address = {dcache_bus_if[0].req_data.addr, 2'b0};
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assign dmem_1_a_bits_address = {dcache_bus_if[1].req_data.addr, 2'b0};
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assign dmem_2_a_bits_address = {dcache_bus_if[2].req_data.addr, 2'b0};
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assign dmem_3_a_bits_address = {dcache_bus_if[3].req_data.addr, 2'b0};
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assign dmem_0_a_bits_data = dcache_bus_if[0].req_data.data;
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assign dmem_1_a_bits_data = dcache_bus_if[1].req_data.data;
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assign dmem_2_a_bits_data = dcache_bus_if[2].req_data.data;
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assign dmem_3_a_bits_data = dcache_bus_if[3].req_data.data;
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assign dmem_0_a_bits_source = dcache_bus_if[0].req_data.tag;
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assign dmem_1_a_bits_source = dcache_bus_if[1].req_data.tag;
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assign dmem_2_a_bits_source = dcache_bus_if[2].req_data.tag;
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assign dmem_3_a_bits_source = dcache_bus_if[3].req_data.tag;
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// we assume all lanes always have the same tag; otherwise the sourceId
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// logic in the Chisel tile breaks
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// always @(*) begin
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// for (i = 0; i < 4; i++) begin
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// assert(dcache_req_if.tag[0] == dcache_req_if.tag[i])
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// end
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// end
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// Translate Vortex rw/byteen to TileLink opcode
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assign dmem_0_a_bits_opcode =
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dcache_bus_if[0].req_data.rw ?
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(&dcache_bus_if[0].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd0 /*FIXME: PutPartial but spoofed to PutFull*/)
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: 3'd4 /*Get*/;
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assign dmem_1_a_bits_opcode =
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dcache_bus_if[1].req_data.rw ?
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(&dcache_bus_if[1].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd0 /*FIXME: PutPartial but spoofed to PutFull*/)
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: 3'd4 /*Get*/;
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assign dmem_2_a_bits_opcode =
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dcache_bus_if[2].req_data.rw ?
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(&dcache_bus_if[2].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd0 /*FIXME: PutPartial but spoofed to PutFull*/)
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: 3'd4 /*Get*/;
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assign dmem_3_a_bits_opcode =
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dcache_bus_if[3].req_data.rw ?
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(&dcache_bus_if[3].req_data.byteen ? 3'd0 /*PutFull*/ : 3'd0 /*FIXME: PutPartial but spoofed to PutFull*/)
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: 3'd4 /*Get*/;
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// Vortex cache requests are single-fixed-size
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// NOTE: MAKE SURE TO CHANGE CONSTANT WIDTH FOR SIZE!
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assign dmem_0_a_bits_size = 4'd2;
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assign dmem_1_a_bits_size = 4'd2;
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assign dmem_2_a_bits_size = 4'd2;
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assign dmem_3_a_bits_size = 4'd2;
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/* $countones(dcache_req_if.byteen[0]) === 'd4 ? 2'd2 :
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($countones(dcache_req_if.byteen[0]) === 'd2 ? 2'd1 : 2'd0); */
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// byteen can be directly used as TL mask
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assign dmem_0_a_bits_mask = dcache_bus_if[0].req_data.byteen;
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assign dmem_1_a_bits_mask = dcache_bus_if[1].req_data.byteen;
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assign dmem_2_a_bits_mask = dcache_bus_if[2].req_data.byteen;
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assign dmem_3_a_bits_mask = dcache_bus_if[3].req_data.byteen;
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assign dcache_bus_if[0].req_ready = dmem_0_a_ready;
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assign dcache_bus_if[1].req_ready = dmem_1_a_ready;
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assign dcache_bus_if[2].req_ready = dmem_2_a_ready;
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assign dcache_bus_if[3].req_ready = dmem_3_a_ready;
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// assign {dmem_3_a_bits_corrupt, dmem_2_a_bits_corrupt, dmem_1_a_bits_corrupt, dmem_0_a_bits_corrupt} = '0;
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// assign {dmem_3_a_bits_param, dmem_2_a_bits_param, dmem_1_a_bits_param, dmem_0_a_bits_param} = '0;
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/* fpu */
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// assign {fpu_hartid, fpu_time, fpu_inst, fpu_fromint_data, fpu_fcsr_rm, fpu_dmem_resp_val, fpu_dmem_resp_type,
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// fpu_dmem_resp_tag, fpu_valid, fpu_killx, fpu_killm, fpu_keep_clock_enabled} = '0;
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assign cease = ~busy;
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assign wfi = 1'b0;
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// TODO: fix this for Vortex 2.0
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// always @(posedge clock) begin
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// for (integer i = 0; i < 4; i++) begin
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// if (dcache_req_if.valid[i] && dcache_req_if.ready[i] && dcache_req_if.rw[i]) begin
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// if ({dcache_req_if.addr[i], 2'b0}[31:28] == 4'hc) begin // heap address
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// $display("[%d] STORE HEAP MEM: CORE=%d, THREAD=%d, ADDRESS=0x%X, DATA=0x%08X",
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// $time(), CORE_ID, i, {dcache_req_if.addr[i], 2'b0}, dcache_req_if.data[i]);
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// end
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// end
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// // if (dcache_rsp_if.valid[i] && dcache_rsp_if.ready) begin
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// // $display("[%d] LOAD HEAP MEM: CORE=%d, THREAD=%d, DATA=0x%08X",
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// // $time(), CORE_ID, i, dcache_rsp_if.data);
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// // end
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// end
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// end
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logic sim_ebreak;
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logic [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value;
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logic [3:0] reset_start_counter;
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logic core_reset;
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logic dcr_reset;
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always @(posedge clock) begin
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if (reset) begin
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reset_start_counter <= 4'ha;
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end else begin
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if (reset_start_counter > 4'h0) begin
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reset_start_counter <= reset_start_counter - 4'h1;
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end
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end
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end
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// Delay reset signal by a few cycles to make time for resetting the DCR
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// (device configuration registers).
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assign core_reset = reset || (reset_start_counter != 4'h0); // || intr_reset;
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assign dcr_reset = !reset && (reset_start_counter != 4'h0);
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// A small FSM that tries to set DCR "properly" in the same order as
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// defined in VX_types.vh.
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//
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// DCR is a device configuration register that holds (among other things)
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// the startup address for the kernel, nominally set to 0x80000000.
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// TODO: Original Vortex code buffers dcr_bus by one cycle when
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// SOCKET_SIZE > 1, as below. Might want to check if we need to do the
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// same
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// `BUFFER_DCR_BUS_IF (core_dcr_bus_if, dcr_bus_if, (`SOCKET_SIZE > 1));
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logic [`VX_DCR_ADDR_BITS-1:0] dcr_state;
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logic [`VX_DCR_ADDR_BITS-1:0] dcr_state_n;
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logic dcr_write_valid;
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logic [`VX_DCR_ADDR_WIDTH-1:0] dcr_write_addr;
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logic [`VX_DCR_DATA_WIDTH-1:0] dcr_write_data;
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always @(posedge clock) begin
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if (reset) begin
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dcr_state <= `VX_DCR_ADDR_BITS'h000;
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end else begin
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dcr_state <= dcr_state_n;
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end
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end
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always @(*) begin
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dcr_state_n = dcr_state;
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dcr_write_valid = 1'b0;
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dcr_write_addr = `VX_DCR_ADDR_WIDTH'b0;
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dcr_write_data = `VX_DCR_DATA_WIDTH'b0;
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|
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case (dcr_state)
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`VX_DCR_ADDR_BITS'h000: begin
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dcr_state_n = `VX_DCR_BASE_STATE_BEGIN;
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end
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`VX_DCR_BASE_STATE_BEGIN: begin
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dcr_state_n = `VX_DCR_BASE_STARTUP_ADDR1;
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|
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dcr_write_valid = 1'b1;
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dcr_write_addr = `VX_DCR_BASE_STARTUP_ADDR0;
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dcr_write_data = BOOTROM_HANG100;
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end
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`VX_DCR_BASE_STARTUP_ADDR1: begin
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dcr_state_n = `VX_DCR_BASE_MPM_CLASS;
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|
|
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dcr_write_valid = 1'b1;
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dcr_write_addr = `VX_DCR_BASE_STARTUP_ADDR1;
|
|
// FIXME: not sure what this does
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|
dcr_write_data = `VX_DCR_DATA_WIDTH'h0;
|
|
end
|
|
`VX_DCR_BASE_MPM_CLASS: begin
|
|
dcr_state_n = `VX_DCR_BASE_STATE_END;
|
|
|
|
dcr_write_valid = 1'b1;
|
|
dcr_write_addr = `VX_DCR_BASE_MPM_CLASS;
|
|
dcr_write_data = `VX_DCR_DATA_WIDTH'h0;
|
|
end
|
|
`VX_DCR_BASE_STATE_END: begin
|
|
dcr_state_n = dcr_state;
|
|
|
|
dcr_write_valid = 1'b0;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
VX_dcr_bus_if dcr_bus_if();
|
|
assign dcr_bus_if.write_valid = dcr_write_valid;
|
|
assign dcr_bus_if.write_addr = dcr_write_addr;
|
|
assign dcr_bus_if.write_data = dcr_write_data;
|
|
|
|
VX_core #(
|
|
.CORE_ID (CORE_ID)
|
|
) core (
|
|
`SCOPE_IO_BIND (0) // TODO: should be socket id
|
|
|
|
.clk (clock),
|
|
.reset (core_reset),
|
|
|
|
`ifdef PERF_ENABLE
|
|
// NOTE unused
|
|
.mem_perf_if (mem_perf_tmp_if),
|
|
`endif
|
|
|
|
.dcr_bus_if (dcr_bus_if),
|
|
|
|
.dcache_bus_if (dcache_bus_if),
|
|
|
|
.icache_bus_if (icache_bus_if),
|
|
|
|
`ifdef GBAR_ENABLE
|
|
// NOTE unused
|
|
.gbar_bus_if (per_core_gbar_bus_if[i]),
|
|
`endif
|
|
|
|
.sim_ebreak (sim_ebreak),
|
|
.sim_wb_value (sim_wb_value),
|
|
.busy (busy)
|
|
);
|
|
|
|
// VX_dcache_req_if #(
|
|
// .NUM_REQS (`DCACHE_NUM_REQS),
|
|
// .WORD_SIZE (`DCACHE_WORD_SIZE),
|
|
// .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH)
|
|
// ) dcache_req_if();
|
|
|
|
// VX_dcache_rsp_if #(
|
|
// .NUM_REQS (`DCACHE_NUM_REQS),
|
|
// .WORD_SIZE (`DCACHE_WORD_SIZE),
|
|
// .TAG_WIDTH (`DCACHE_CORE_TAG_WIDTH)
|
|
// ) dcache_rsp_if();
|
|
//
|
|
// VX_icache_req_if #(
|
|
// .WORD_SIZE (`ICACHE_WORD_SIZE),
|
|
// .TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH)
|
|
// ) icache_req_if();
|
|
|
|
// VX_icache_rsp_if #(
|
|
// .WORD_SIZE (`ICACHE_WORD_SIZE),
|
|
// .TAG_WIDTH (`ICACHE_CORE_TAG_WIDTH)
|
|
// ) icache_rsp_if();
|
|
|
|
// VX_pipeline #(
|
|
// .CORE_ID(CORE_ID)
|
|
// ) pipeline (
|
|
// `SCOPE_BIND_VX_core_pipeline
|
|
// `ifdef PERF_ENABLE
|
|
// .perf_memsys_if (perf_memsys_if),
|
|
// `endif
|
|
|
|
// .clk(clock),
|
|
// .reset(reset || intr_reset),
|
|
|
|
// .irq(1'b0/*intr_reset*/),
|
|
|
|
// // Dcache core request
|
|
// .dcache_req_valid (dcache_req_if.valid),
|
|
// .dcache_req_rw (dcache_req_if.rw),
|
|
// .dcache_req_byteen (dcache_req_if.byteen),
|
|
// .dcache_req_addr (dcache_req_if.addr),
|
|
// .dcache_req_data (dcache_req_if.data),
|
|
// .dcache_req_tag (dcache_req_if.tag),
|
|
// .dcache_req_ready (dcache_req_if.ready),
|
|
|
|
// // Dcache core reponse
|
|
// .dcache_rsp_valid (dcache_rsp_if.valid),
|
|
// .dcache_rsp_tmask (dcache_rsp_if.tmask),
|
|
// .dcache_rsp_data (dcache_rsp_if.data),
|
|
// .dcache_rsp_tag (dcache_rsp_if.tag),
|
|
// .dcache_rsp_ready (dcache_rsp_if.ready),
|
|
|
|
// // Icache core request
|
|
// .icache_req_valid (icache_req_if.valid),
|
|
// .icache_req_addr (icache_req_if.addr),
|
|
// .icache_req_tag (icache_req_if.tag),
|
|
// .icache_req_ready (icache_req_if.ready),
|
|
|
|
// // Icache core reponse
|
|
// .icache_rsp_valid (icache_rsp_if.valid),
|
|
// .icache_rsp_data (icache_rsp_if.data),
|
|
// .icache_rsp_tag (icache_rsp_if.tag),
|
|
// .icache_rsp_ready (icache_rsp_if.ready),
|
|
|
|
// // Status
|
|
// .busy(busy)
|
|
// );
|
|
|
|
always @(*) begin
|
|
if (busy === 1'b0) begin
|
|
$display("no more active warps");
|
|
|
|
@(negedge clock);
|
|
|
|
// TODO: lane assumed to be 4
|
|
// `ifndef SYNTHESIS
|
|
// for (integer j = 0; j < `NUM_WARPS; j++) begin
|
|
// $display("warp %2d", j);
|
|
// for (integer k = 0; k < `NUM_REGS; k += 1)
|
|
// $display("x%2d: %08x %08x %08x %08x", k,
|
|
// pipeline.issue.gpr_stage.iports[/*thread*/0].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k],
|
|
// pipeline.issue.gpr_stage.iports[/*thread*/1].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k],
|
|
// pipeline.issue.gpr_stage.iports[/*thread*/2].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k],
|
|
// pipeline.issue.gpr_stage.iports[/*thread*/3].dp_ram1.not_out_reg.reg_dump.ram[j * `NUM_REGS + k]);
|
|
// end
|
|
// `endif
|
|
|
|
// @(posedge clock) $finish();
|
|
end
|
|
end
|
|
|
|
endmodule : Vortex
|
|
|
|
|
|
|
|
|
|
|