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Assert ready when write response is coming back

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Since the core's response ready signal depends on response valid, but core does
not accept write ACKs, we need to manually assert ready when there is a valid
response coming in for a write regardless of the core's ready state (which would
be 0).
This commit is contained in:
Hansung Kim
2023-11-17 19:08:32 -08:00
parent 90e21e8e58
commit faf5fe3838
1 changed files with 6 additions and 4 deletions
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10
hw/rtl/VX_core_wrapper.sv
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@@ -268,10 +268,12 @@ module Vortex import VX_gpu_pkg::*; #(
assign dcache_bus_if[2].rsp_data.tag = dmem_2_d_bits_source;
assign dcache_bus_if[3].rsp_data.tag = dmem_3_d_bits_source;
assign dmem_0_d_ready = dcache_bus_if[0].rsp_ready;
assign dmem_1_d_ready = dcache_bus_if[1].rsp_ready;
assign dmem_2_d_ready = dcache_bus_if[2].rsp_ready;
assign dmem_3_d_ready = dcache_bus_if[3].rsp_ready;
// When there's a write ACK coming back, ready bit should always be 1 to
// accept them because core does not accept them on their own
assign dmem_0_d_ready = dcache_bus_if[0].rsp_ready || (dmem_0_d_bits_opcode == 3'd0 /*AccessAck*/);
assign dmem_1_d_ready = dcache_bus_if[1].rsp_ready || (dmem_1_d_bits_opcode == 3'd0 /*AccessAck*/);
assign dmem_2_d_ready = dcache_bus_if[2].rsp_ready || (dmem_2_d_bits_opcode == 3'd0 /*AccessAck*/);
assign dmem_3_d_ready = dcache_bus_if[3].rsp_ready || (dmem_3_d_bits_opcode == 3'd0 /*AccessAck*/);
assign dmem_0_a_valid = dcache_bus_if[0].req_valid;
assign dmem_1_a_valid = dcache_bus_if[1].req_valid;