132 lines
5.2 KiB
Verilog
132 lines
5.2 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache_miss_resrv #(
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 0,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 0,
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// Size of a word in bytes
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parameter WORD_SIZE = 0,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 0,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 0,
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// caceh requests tag size
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parameter CORE_TAG_WIDTH = 0
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) (
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input wire clk,
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input wire reset,
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// Miss enqueue
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input wire miss_add,
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input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
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input wire[`BASE_ADDR_BITS-1:0] miss_add_wsel,
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input wire[`WORD_WIDTH-1:0] miss_add_data,
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input wire[`REQS_BITS-1:0] miss_add_tid,
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input wire[CORE_TAG_WIDTH-1:0] miss_add_tag,
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input wire[`BYTE_EN_BITS-1:0] miss_add_mem_read,
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input wire[`BYTE_EN_BITS-1:0] miss_add_mem_write,
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input wire mrvq_init_ready_state,
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input wire miss_add_is_snp,
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output wire miss_resrv_full,
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output wire miss_resrv_stop,
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// Broadcast Address
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input wire is_fill_st1,
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input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st1,
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output wire pending_hazard,
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// Miss dequeue
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input wire miss_resrv_pop,
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output wire miss_resrv_valid_st0,
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output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
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output wire[`BASE_ADDR_BITS-1:0] miss_resrv_wsel_st0,
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output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
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output wire[`REQS_BITS-1:0] miss_resrv_tid_st0,
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output wire[CORE_TAG_WIDTH-1:0] miss_resrv_tag_st0,
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output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_read_st0,
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output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_write_st0,
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output wire miss_resrv_is_snp_st0
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);
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reg [`MRVQ_METADATA_WIDTH-1:0] metadata_table[MRVQ_SIZE-1:0];
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reg [MRVQ_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
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reg [MRVQ_SIZE-1:0] valid_table;
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reg [MRVQ_SIZE-1:0] ready_table;
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reg [`LOG2UP(MRVQ_SIZE)-1:0] head_ptr;
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reg [`LOG2UP(MRVQ_SIZE)-1:0] tail_ptr;
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reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
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assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
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assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5));
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wire enqueue_possible = !miss_resrv_full;
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wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
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reg [MRVQ_SIZE-1:0] make_ready;
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reg [MRVQ_SIZE-1:0] valid_address_match;
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genvar i;
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generate
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for (i = 0; i < MRVQ_SIZE; i++) begin
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assign valid_address_match[i] = valid_table[i] && (addr_table[i] == fill_addr_st1);
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assign make_ready[i] = is_fill_st1 && valid_address_match[i];
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end
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endgenerate
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assign pending_hazard = |(valid_address_match);
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wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr];
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wire [`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = head_ptr;
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assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible;
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assign miss_resrv_addr_st0 = addr_table[dequeue_index];
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assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0, miss_resrv_wsel_st0, miss_resrv_is_snp_st0} = metadata_table[dequeue_index];
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wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2);
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wire mrvq_pop = miss_resrv_pop && dequeue_possible;
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wire update_ready = (| make_ready);
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always @(posedge clk) begin
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if (reset) begin
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valid_table <= 0;
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ready_table <= 0;
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size <= 0;
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head_ptr <= 0;
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tail_ptr <= 0;
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end else begin
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if (mrvq_push) begin
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valid_table[enqueue_index] <= 1;
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ready_table[enqueue_index] <= mrvq_init_ready_state;
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addr_table[enqueue_index] <= miss_add_addr;
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metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_wsel, miss_add_is_snp};
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tail_ptr <= tail_ptr + 1;
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end
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// update entry as 'ready' during DRAM fill response
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if (update_ready) begin
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ready_table <= ready_table | make_ready;
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end
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if (mrvq_pop) begin
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valid_table[dequeue_index] <= 0;
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ready_table[dequeue_index] <= 0;
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addr_table[dequeue_index] <= 0;
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metadata_table[dequeue_index] <= 0;
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head_ptr <= head_ptr + 1;
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end
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if (!(mrvq_push && mrvq_pop)) begin
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if (mrvq_push) begin
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size <= size + 1;
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end
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if (mrvq_pop) begin
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size <= size - 1;
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end
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end
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end
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end
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endmodule |