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Added an initial ready state to an mrvq entry that might be set to 1

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This commit is contained in:
felsabbagh3
2020-05-12 21:47:51 -07:00
parent 5b2624046e
commit ff140b6811
3 changed files with 27 additions and 15 deletions
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24
hw/rtl/cache/VX_bank.v vendored
View File

@@ -355,6 +355,7 @@ module VX_bank #(
wire fill_saw_dirty_st1e;
wire is_snp_st1e;
wire snp_to_mrvq_st1e;
wire mrvq_init_ready_state_st1e;
assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1];
assign {tag_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
@@ -396,13 +397,14 @@ module VX_bank #(
.is_snp_st1e (is_snp_st1e),
// Read Data
.readword_st1e (readword_st1e),
.readdata_st1e (readdata_st1e),
.readtag_st1e (readtag_st1e),
.miss_st1e (miss_st1e),
.dirty_st1e (dirty_st1e),
.fill_saw_dirty_st1e(fill_saw_dirty_st1e),
.snp_to_mrvq_st1e (snp_to_mrvq_st1e)
.readword_st1e (readword_st1e),
.readdata_st1e (readdata_st1e),
.readtag_st1e (readtag_st1e),
.miss_st1e (miss_st1e),
.dirty_st1e (dirty_st1e),
.fill_saw_dirty_st1e (fill_saw_dirty_st1e),
.snp_to_mrvq_st1e (snp_to_mrvq_st1e),
.mrvq_init_ready_state_st1e(mrvq_init_ready_state_st1e)
);
wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1];
@@ -420,16 +422,17 @@ module VX_bank #(
wire [SNP_REQ_TAG_WIDTH-1:0] snrq_tag_st2;
wire is_snp_st2;
wire snp_to_mrvq_st2;
wire mrvq_init_ready_state_st2;
VX_generic_register #(
.N(1+ 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH + SNP_REQ_TAG_WIDTH)
.N(1+1+ 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH + SNP_REQ_TAG_WIDTH)
) st_1e_2 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({snp_to_mrvq_st1e, is_snp_st1e, snrq_tag_st1[STAGE_1_CYCLES-1], fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({snp_to_mrvq_st2 , is_snp_st2 , snrq_tag_st2, fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
.in ({mrvq_init_ready_state_st1e, snp_to_mrvq_st1e, is_snp_st1e, snrq_tag_st1[STAGE_1_CYCLES-1], fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({mrvq_init_ready_state_st2, snp_to_mrvq_st2 , is_snp_st2 , snrq_tag_st2, fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
);
@@ -484,6 +487,7 @@ module VX_bank #(
.miss_add_is_snp (miss_add_is_snp),
.miss_resrv_full (mrvq_full),
.miss_resrv_stop (mrvq_stop),
.mrvq_init_ready_state (mrvq_init_ready_state_st2),
// Broadcast
.is_fill_st1 (is_fill_st1[STAGE_1_CYCLES-1]),

3
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -26,6 +26,7 @@ module VX_cache_miss_resrv #(
input wire[CORE_TAG_WIDTH-1:0] miss_add_tag,
input wire[`BYTE_EN_BITS-1:0] miss_add_mem_read,
input wire[`BYTE_EN_BITS-1:0] miss_add_mem_write,
input wire mrvq_init_ready_state,
input wire miss_add_is_snp,
output wire miss_resrv_full,
output wire miss_resrv_stop,
@@ -98,7 +99,7 @@ module VX_cache_miss_resrv #(
end else begin
if (mrvq_push) begin
valid_table[enqueue_index] <= 1;
ready_table[enqueue_index] <= 0;
ready_table[enqueue_index] <= mrvq_init_ready_state;
addr_table[enqueue_index] <= miss_add_addr;
metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_wsel, miss_add_is_snp};
tail_ptr <= tail_ptr + 1;

15
hw/rtl/cache/VX_tag_data_access.v vendored
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@@ -47,7 +47,8 @@ module VX_tag_data_access #(
output wire miss_st1e,
output wire dirty_st1e,
output wire fill_saw_dirty_st1e,
output wire snp_to_mrvq_st1e
output wire snp_to_mrvq_st1e,
output wire mrvq_init_ready_state_st1e
);
reg read_valid_st1c[STAGE_1_CYCLES-1:0];
@@ -236,10 +237,16 @@ module VX_tag_data_access #(
wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e;
wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && !tags_match;
wire real_miss = req_invalid || req_miss || (force_request_miss_st1e && !is_snp_st1e);
wire real_miss = req_invalid || req_miss;
wire force_core_miss = (force_request_miss_st1e && !is_snp_st1e && !writefill_st1e && valid_req_st1e && !real_miss);
assign snp_to_mrvq_st1e = valid_req_st1e && is_snp_st1e && force_request_miss_st1e;
assign miss_st1e = real_miss || snoop_hit_no_pending;
assign snp_to_mrvq_st1e = valid_req_st1e && is_snp_st1e && force_request_miss_st1e;
assign mrvq_init_ready_state_st1e = snp_to_mrvq_st1e || force_core_miss;
assign miss_st1e = real_miss || snoop_hit_no_pending || force_core_miss;
assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e;
assign readdata_st1e = use_read_data_st1e;
assign readtag_st1e = use_read_tag_st1e;