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Add constraint file and display module

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CGH0S7
2024-12-28 09:05:23 +08:00
parent 66cda81233
commit 320f71ac96
3 changed files with 501 additions and 399 deletions
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// Generated by CIRCT firtool-1.62.0 // Generated by CIRCT firtool-1.62.0
// VCS coverage exclude_file // VCS coverage exclude_file
module regfile_32x32( module regfile_32x32(
input [4:0] R0_addr, input [4:0] R0_addr,
input R0_en, input R0_en,
R0_clk, R0_clk,
output [31:0] R0_data, output [31:0] R0_data,
input [4:0] R1_addr, input [4:0] R1_addr,
input R1_en, input R1_en,
R1_clk, R1_clk,
output [31:0] R1_data, output [31:0] R1_data,
input [4:0] W0_addr, input [4:0] W0_addr,
input W0_en, input W0_en,
W0_clk, W0_clk,
input [31:0] W0_data input [31:0] W0_data
); );
reg [31:0] Memory[0:31]; reg [31:0] Memory[0:31];
reg _R0_en_d0; reg _R0_en_d0;
reg [4:0] _R0_addr_d0; reg [4:0] _R0_addr_d0;
always @(posedge R0_clk) begin always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en; _R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr; _R0_addr_d0 <= R0_addr;
end // always @(posedge) end // always @(posedge)
reg _R1_en_d0; reg _R1_en_d0;
reg [4:0] _R1_addr_d0; reg [4:0] _R1_addr_d0;
always @(posedge R1_clk) begin always @(posedge R1_clk) begin
_R1_en_d0 <= R1_en; _R1_en_d0 <= R1_en;
_R1_addr_d0 <= R1_addr; _R1_addr_d0 <= R1_addr;
end // always @(posedge) end // always @(posedge)
always @(posedge W0_clk) begin always @(posedge W0_clk) begin
if (W0_en & 1'h1) if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data; Memory[W0_addr] <= W0_data;
end // always @(posedge) end // always @(posedge)
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx; assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx; assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
// DynamicDisplay show_reg()
endmodule endmodule
module Core( module Core(
input clock, input clock,
reset, reset,
output [31:0] io_imem_addr, output [31:0] io_imem_addr,
input [31:0] io_imem_inst, input [31:0] io_imem_inst,
output [31:0] io_dmem_addr, output [31:0] io_dmem_addr,
input [31:0] io_dmem_rdata, input [31:0] io_dmem_rdata,
output io_dmem_wen, output io_dmem_wen,
output [31:0] io_dmem_wdata, output [31:0] io_dmem_wdata,
output io_exit output io_exit
); );
wire [31:0] _regfile_ext_R0_data; wire [31:0] _regfile_ext_R0_data;
wire [31:0] _regfile_ext_R1_data; wire [31:0] _regfile_ext_R1_data;
reg [31:0] id_reg_pc; reg [31:0] id_reg_pc;
reg [31:0] id_reg_inst; reg [31:0] id_reg_inst;
reg [31:0] exe_reg_pc; reg [31:0] exe_reg_pc;
reg [4:0] exe_reg_wb_addr; reg [4:0] exe_reg_wb_addr;
reg [31:0] exe_reg_op1_data; reg [31:0] exe_reg_op1_data;
reg [31:0] exe_reg_op2_data; reg [31:0] exe_reg_op2_data;
reg [31:0] exe_reg_rs2_data; reg [31:0] exe_reg_rs2_data;
reg [4:0] exe_reg_exe_fun; reg [4:0] exe_reg_exe_fun;
reg [1:0] exe_reg_mem_wen; reg [1:0] exe_reg_mem_wen;
reg [1:0] exe_reg_rf_wen; reg [1:0] exe_reg_rf_wen;
reg [2:0] exe_reg_wb_sel; reg [2:0] exe_reg_wb_sel;
reg [31:0] exe_reg_imm_b_sext; reg [31:0] exe_reg_imm_b_sext;
reg [31:0] mem_reg_pc; reg [31:0] mem_reg_pc;
reg [4:0] mem_reg_wb_addr; reg [4:0] mem_reg_wb_addr;
reg [31:0] mem_reg_alu_out; reg [31:0] mem_reg_alu_out;
reg [31:0] mem_reg_rs2_data; reg [31:0] mem_reg_rs2_data;
reg [1:0] mem_reg_rf_wen; reg [1:0] mem_reg_rf_wen;
reg [2:0] mem_reg_wb_sel; reg [2:0] mem_reg_wb_sel;
reg [1:0] mem_reg_mem_wen; reg [1:0] mem_reg_mem_wen;
reg [4:0] wb_reg_wb_addr; reg [4:0] wb_reg_wb_addr;
reg [1:0] wb_reg_rf_wen; reg [1:0] wb_reg_rf_wen;
reg [31:0] wb_reg_wb_data; reg [31:0] wb_reg_wb_data;
reg [31:0] if_reg_pc; reg [31:0] if_reg_pc;
wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1; wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
wire exe_br_flg = wire exe_br_flg =
exe_reg_exe_fun == 5'hC exe_reg_exe_fun == 5'hC
? exe_reg_op1_data != exe_reg_op2_data ? exe_reg_op1_data != exe_reg_op2_data
: exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data; : exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data;
wire exe_jmp_flg = exe_reg_wb_sel == 3'h3; wire exe_jmp_flg = exe_reg_wb_sel == 3'h3;
always @(posedge clock) begin always @(posedge clock) begin
automatic logic _id_inst_T = exe_br_flg | exe_jmp_flg; automatic logic _id_inst_T = exe_br_flg | exe_jmp_flg;
automatic logic _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1; automatic logic _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
automatic logic stall_flg; automatic logic stall_flg;
automatic logic [31:0] id_inst; automatic logic [31:0] id_inst;
automatic logic _id_rs2_data_T_2; automatic logic _id_rs2_data_T_2;
automatic logic _id_rs2_data_T; automatic logic _id_rs2_data_T;
automatic logic [31:0] _id_rs2_data_T_8; automatic logic [31:0] _id_rs2_data_T_8;
automatic logic [16:0] _GEN; automatic logic [16:0] _GEN;
automatic logic _csignals_T_5; automatic logic _csignals_T_5;
automatic logic [19:0] _GEN_0; automatic logic [19:0] _GEN_0;
automatic logic _csignals_T_7; automatic logic _csignals_T_7;
automatic logic _csignals_T_9; automatic logic _csignals_T_9;
automatic logic _csignals_T_11; automatic logic _csignals_T_11;
automatic logic _csignals_T_13; automatic logic _csignals_T_13;
automatic logic _csignals_T_15; automatic logic _csignals_T_15;
automatic logic _csignals_T_17; automatic logic _csignals_T_17;
automatic logic _csignals_T_19; automatic logic _csignals_T_19;
automatic logic [16:0] _GEN_1; automatic logic [16:0] _GEN_1;
automatic logic _csignals_T_21; automatic logic _csignals_T_21;
automatic logic _csignals_T_23; automatic logic _csignals_T_23;
automatic logic _csignals_T_25; automatic logic _csignals_T_25;
automatic logic _csignals_T_27; automatic logic _csignals_T_27;
automatic logic _csignals_T_29; automatic logic _csignals_T_29;
automatic logic _csignals_T_31; automatic logic _csignals_T_31;
automatic logic _csignals_T_33; automatic logic _csignals_T_33;
automatic logic _csignals_T_35; automatic logic _csignals_T_35;
automatic logic _csignals_T_37; automatic logic _csignals_T_37;
automatic logic _csignals_T_39; automatic logic _csignals_T_39;
automatic logic _GEN_2; automatic logic _GEN_2;
automatic logic _GEN_3; automatic logic _GEN_3;
automatic logic [1:0] csignals_1; automatic logic [1:0] csignals_1;
automatic logic [2:0] _csignals_T_95; automatic logic [2:0] _csignals_T_95;
automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]}; automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
automatic logic [62:0] _exe_alu_out_T_8 = automatic logic [62:0] _exe_alu_out_T_8 =
{31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0]; {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
automatic logic [31:0] exe_alu_out; automatic logic [31:0] exe_alu_out;
stall_flg = stall_flg =
_id_rs2_data_hazard_T & (|(id_reg_inst[25:21])) _id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr; & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst; id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
_id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1; _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
_id_rs2_data_T = id_reg_inst[20:16] == 5'h0; _id_rs2_data_T = id_reg_inst[20:16] == 5'h0;
_id_rs2_data_T_8 = _id_rs2_data_T_8 =
id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2 id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
? mem_reg_alu_out ? mem_reg_alu_out
: id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5 : id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
? wb_reg_wb_data ? wb_reg_wb_data
: _regfile_ext_R0_data; : _regfile_ext_R0_data;
_GEN = {id_inst[31:26], id_inst[10:0]}; _GEN = {id_inst[31:26], id_inst[10:0]};
_csignals_T_5 = _GEN == 17'h20; _csignals_T_5 = _GEN == 17'h20;
_GEN_0 = {id_inst[31:28], id_inst[15:0]}; _GEN_0 = {id_inst[31:28], id_inst[15:0]};
_csignals_T_7 = _GEN_0 == 20'h80000; _csignals_T_7 = _GEN_0 == 20'h80000;
_csignals_T_9 = _GEN == 17'h22; _csignals_T_9 = _GEN == 17'h22;
_csignals_T_11 = _GEN == 17'h24; _csignals_T_11 = _GEN == 17'h24;
_csignals_T_13 = _GEN == 17'h25; _csignals_T_13 = _GEN == 17'h25;
_csignals_T_15 = _GEN == 17'h26; _csignals_T_15 = _GEN == 17'h26;
_csignals_T_17 = _GEN_0 == 20'hC0000; _csignals_T_17 = _GEN_0 == 20'hC0000;
_csignals_T_19 = _GEN_0 == 20'hD0000; _csignals_T_19 = _GEN_0 == 20'hD0000;
_GEN_1 = {id_inst[30:20], id_inst[5:0]}; _GEN_1 = {id_inst[30:20], id_inst[5:0]};
_csignals_T_21 = _GEN_1 == 17'h0; _csignals_T_21 = _GEN_1 == 17'h0;
_csignals_T_23 = _GEN_1 == 17'h2; _csignals_T_23 = _GEN_1 == 17'h2;
_csignals_T_25 = _GEN_1 == 17'h3; _csignals_T_25 = _GEN_1 == 17'h3;
_csignals_T_27 = _GEN == 17'h2A; _csignals_T_27 = _GEN == 17'h2A;
_csignals_T_29 = _GEN_0 == 20'h40000; _csignals_T_29 = _GEN_0 == 20'h40000;
_csignals_T_31 = _GEN_0 == 20'h50000; _csignals_T_31 = _GEN_0 == 20'h50000;
_csignals_T_33 = id_inst == 32'hC000000; _csignals_T_33 = id_inst == 32'hC000000;
_csignals_T_35 = _GEN_0 == 20'h8; _csignals_T_35 = _GEN_0 == 20'h8;
_csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000; _csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
_csignals_T_39 = id_inst == 32'h0; _csignals_T_39 = id_inst == 32'h0;
_GEN_2 = _csignals_T_29 | _csignals_T_31; _GEN_2 = _csignals_T_29 | _csignals_T_31;
_GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2; _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
csignals_1 = csignals_1 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
? 2'h0 ? 2'h0
: _csignals_T_33 : _csignals_T_33
? 2'h1 ? 2'h1
: _csignals_T_35 ? 2'h0 : {_csignals_T_37 | _csignals_T_39, 1'h0}; : _csignals_T_35 ? 2'h0 : {_csignals_T_37 | _csignals_T_39, 1'h0};
_csignals_T_95 = _csignals_T_95 =
_csignals_T_5 _csignals_T_5
? 3'h1 ? 3'h1
: _csignals_T_7 : _csignals_T_7
? 3'h2 ? 3'h2
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
? 3'h1 ? 3'h1
: _csignals_T_17 | _csignals_T_19 : _csignals_T_17 | _csignals_T_19
? 3'h2 ? 3'h2
: _GEN_3 : _GEN_3
? 3'h1 ? 3'h1
: _csignals_T_33 : _csignals_T_33
? 3'h4 ? 3'h4
: _csignals_T_35 : _csignals_T_35
? 3'h0 ? 3'h0
: _csignals_T_37 ? 3'h5 : {2'h0, ~_csignals_T_39}; : _csignals_T_37 ? 3'h5 : {2'h0, ~_csignals_T_39};
exe_alu_out = exe_alu_out =
exe_reg_exe_fun == 5'hE exe_reg_exe_fun == 5'hE
? exe_reg_op1_data ? exe_reg_op1_data
: exe_reg_exe_fun == 5'h9 : exe_reg_exe_fun == 5'h9
? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)} ? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
: exe_reg_exe_fun == 5'h8 : exe_reg_exe_fun == 5'h8
? $signed($signed(exe_reg_op1_data) >>> _GEN_4) ? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
: exe_reg_exe_fun == 5'h7 : exe_reg_exe_fun == 5'h7
? exe_reg_op1_data >> _GEN_4 ? exe_reg_op1_data >> _GEN_4
: exe_reg_exe_fun == 5'h6 : exe_reg_exe_fun == 5'h6
? _exe_alu_out_T_8[31:0] ? _exe_alu_out_T_8[31:0]
: exe_reg_exe_fun == 5'h5 : exe_reg_exe_fun == 5'h5
? exe_reg_op1_data ^ exe_reg_op2_data ? exe_reg_op1_data ^ exe_reg_op2_data
: exe_reg_exe_fun == 5'h4 : exe_reg_exe_fun == 5'h4
? exe_reg_op1_data | exe_reg_op2_data ? exe_reg_op1_data | exe_reg_op2_data
: exe_reg_exe_fun == 5'h3 : exe_reg_exe_fun == 5'h3
? exe_reg_op1_data & exe_reg_op2_data ? exe_reg_op1_data & exe_reg_op2_data
: exe_reg_exe_fun == 5'h2 : exe_reg_exe_fun == 5'h2
? exe_reg_op1_data - exe_reg_op2_data ? exe_reg_op1_data - exe_reg_op2_data
: exe_reg_exe_fun == 5'h1 : exe_reg_exe_fun == 5'h1
? exe_reg_op1_data + exe_reg_op2_data ? exe_reg_op1_data + exe_reg_op2_data
: 32'h0; : 32'h0;
if (~stall_flg) if (~stall_flg)
id_reg_pc <= if_reg_pc; id_reg_pc <= if_reg_pc;
if (_id_inst_T) if (_id_inst_T)
id_reg_inst <= 32'h0; id_reg_inst <= 32'h0;
else if (~stall_flg) else if (~stall_flg)
id_reg_inst <= io_imem_inst; id_reg_inst <= io_imem_inst;
exe_reg_pc <= id_reg_pc; exe_reg_pc <= id_reg_pc;
exe_reg_wb_addr <= id_reg_inst[15:11]; exe_reg_wb_addr <= id_reg_inst[15:11];
if (csignals_1 == 2'h0) if (csignals_1 == 2'h0)
exe_reg_op1_data <= exe_reg_op1_data <=
id_reg_inst[25:21] == 5'h0 id_reg_inst[25:21] == 5'h0
? 32'h0 ? 32'h0
: id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2 : id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
? mem_reg_alu_out ? mem_reg_alu_out
: id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5 : id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
? wb_reg_wb_data ? wb_reg_wb_data
: _regfile_ext_R1_data; : _regfile_ext_R1_data;
else if (csignals_1 == 2'h1) else if (csignals_1 == 2'h1)
exe_reg_op1_data <= id_reg_pc; exe_reg_op1_data <= id_reg_pc;
else else
exe_reg_op1_data <= 32'h0; exe_reg_op1_data <= 32'h0;
if (_csignals_T_95 == 3'h5) if (_csignals_T_95 == 3'h5)
exe_reg_op2_data <= {id_inst[15:0], 16'h0}; exe_reg_op2_data <= {id_inst[15:0], 16'h0};
else if (_csignals_T_95 == 3'h4) else if (_csignals_T_95 == 3'h4)
exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0}; exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
else if (_csignals_T_95 == 3'h3 | _csignals_T_95 == 3'h2) else if (_csignals_T_95 == 3'h3 | _csignals_T_95 == 3'h2)
exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]}; exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
else if (_csignals_T_95 != 3'h1 | _id_rs2_data_T) else if (_csignals_T_95 != 3'h1 | _id_rs2_data_T)
exe_reg_op2_data <= 32'h0; exe_reg_op2_data <= 32'h0;
else else
exe_reg_op2_data <= _id_rs2_data_T_8; exe_reg_op2_data <= _id_rs2_data_T_8;
exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8; exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8;
if (_csignals_T_5 | _csignals_T_7) if (_csignals_T_5 | _csignals_T_7)
exe_reg_exe_fun <= 5'h1; exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_9) else if (_csignals_T_9)
exe_reg_exe_fun <= 5'h2; exe_reg_exe_fun <= 5'h2;
else if (_csignals_T_11) else if (_csignals_T_11)
exe_reg_exe_fun <= 5'h3; exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_13) else if (_csignals_T_13)
exe_reg_exe_fun <= 5'h4; exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_15) else if (_csignals_T_15)
exe_reg_exe_fun <= 5'h5; exe_reg_exe_fun <= 5'h5;
else if (_csignals_T_17) else if (_csignals_T_17)
exe_reg_exe_fun <= 5'h3; exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_19) else if (_csignals_T_19)
exe_reg_exe_fun <= 5'h4; exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_21) else if (_csignals_T_21)
exe_reg_exe_fun <= 5'h6; exe_reg_exe_fun <= 5'h6;
else if (_csignals_T_23) else if (_csignals_T_23)
exe_reg_exe_fun <= 5'h7; exe_reg_exe_fun <= 5'h7;
else if (_csignals_T_25) else if (_csignals_T_25)
exe_reg_exe_fun <= 5'h8; exe_reg_exe_fun <= 5'h8;
else if (_csignals_T_27) else if (_csignals_T_27)
exe_reg_exe_fun <= 5'h9; exe_reg_exe_fun <= 5'h9;
else if (_csignals_T_29) else if (_csignals_T_29)
exe_reg_exe_fun <= 5'hB; exe_reg_exe_fun <= 5'hB;
else if (_csignals_T_31) else if (_csignals_T_31)
exe_reg_exe_fun <= 5'hC; exe_reg_exe_fun <= 5'hC;
else if (_csignals_T_33) else if (_csignals_T_33)
exe_reg_exe_fun <= 5'h1; exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_35) else if (_csignals_T_35)
exe_reg_exe_fun <= 5'hE; exe_reg_exe_fun <= 5'hE;
else else
exe_reg_exe_fun <= {4'h0, _csignals_T_37}; exe_reg_exe_fun <= {4'h0, _csignals_T_37};
exe_reg_mem_wen <= 2'h0; exe_reg_mem_wen <= 2'h0;
if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
| _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin | _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
exe_reg_rf_wen <= 2'h1; exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h1; exe_reg_wb_sel <= 3'h1;
end end
else if (_GEN_2) begin else if (_GEN_2) begin
exe_reg_rf_wen <= 2'h0; exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0; exe_reg_wb_sel <= 3'h0;
end end
else if (_csignals_T_33) begin else if (_csignals_T_33) begin
exe_reg_rf_wen <= 2'h1; exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h3; exe_reg_wb_sel <= 3'h3;
end end
else if (_csignals_T_35) begin else if (_csignals_T_35) begin
exe_reg_rf_wen <= 2'h0; exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0; exe_reg_wb_sel <= 3'h0;
end end
else begin else begin
exe_reg_rf_wen <= {1'h0, _csignals_T_37}; exe_reg_rf_wen <= {1'h0, _csignals_T_37};
exe_reg_wb_sel <= {2'h0, _csignals_T_37}; exe_reg_wb_sel <= {2'h0, _csignals_T_37};
end end
exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]}; exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
mem_reg_pc <= exe_reg_pc; mem_reg_pc <= exe_reg_pc;
mem_reg_wb_addr <= exe_reg_wb_addr; mem_reg_wb_addr <= exe_reg_wb_addr;
mem_reg_alu_out <= exe_alu_out; mem_reg_alu_out <= exe_alu_out;
mem_reg_rs2_data <= exe_reg_rs2_data; mem_reg_rs2_data <= exe_reg_rs2_data;
mem_reg_rf_wen <= exe_reg_rf_wen; mem_reg_rf_wen <= exe_reg_rf_wen;
mem_reg_wb_sel <= exe_reg_wb_sel; mem_reg_wb_sel <= exe_reg_wb_sel;
mem_reg_mem_wen <= exe_reg_mem_wen; mem_reg_mem_wen <= exe_reg_mem_wen;
wb_reg_wb_addr <= mem_reg_wb_addr; wb_reg_wb_addr <= mem_reg_wb_addr;
wb_reg_rf_wen <= mem_reg_rf_wen; wb_reg_rf_wen <= mem_reg_rf_wen;
wb_reg_wb_data <= wb_reg_wb_data <=
mem_reg_wb_sel == 3'h3 mem_reg_wb_sel == 3'h3
? mem_reg_pc + 32'h4 ? mem_reg_pc + 32'h4
: mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out; : mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out;
if (reset) if (reset)
if_reg_pc <= 32'h0; if_reg_pc <= 32'h0;
else if (exe_br_flg) else if (exe_br_flg)
if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext; if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
else if (exe_jmp_flg) else if (exe_jmp_flg)
if_reg_pc <= exe_alu_out; if_reg_pc <= exe_alu_out;
else if (~stall_flg) else if (~stall_flg)
if_reg_pc <= if_reg_pc + 32'h4; if_reg_pc <= if_reg_pc + 32'h4;
end // always @(posedge) end // always @(posedge)
regfile_32x32 regfile_ext ( regfile_32x32 regfile_ext (
.R0_addr (id_reg_inst[20:16]), .R0_addr (id_reg_inst[20:16]),
.R0_en (1'h1), .R0_en (1'h1),
.R0_clk (clock), .R0_clk (clock),
.R0_data (_regfile_ext_R0_data), .R0_data (_regfile_ext_R0_data),
.R1_addr (id_reg_inst[25:21]), .R1_addr (id_reg_inst[25:21]),
.R1_en (1'h1), .R1_en (1'h1),
.R1_clk (clock), .R1_clk (clock),
.R1_data (_regfile_ext_R1_data), .R1_data (_regfile_ext_R1_data),
.W0_addr (wb_reg_wb_addr), .W0_addr (wb_reg_wb_addr),
.W0_en (_id_rs2_data_T_5), .W0_en (_id_rs2_data_T_5),
.W0_clk (clock), .W0_clk (clock),
.W0_data (wb_reg_wb_data) .W0_data (wb_reg_wb_data)
); );
assign io_imem_addr = if_reg_pc; assign io_imem_addr = if_reg_pc;
assign io_dmem_addr = mem_reg_alu_out; assign io_dmem_addr = mem_reg_alu_out;
assign io_dmem_wen = mem_reg_mem_wen[0]; assign io_dmem_wen = mem_reg_mem_wen[0];
assign io_dmem_wdata = mem_reg_rs2_data; assign io_dmem_wdata = mem_reg_rs2_data;
assign io_exit = id_reg_inst == 32'hC0000000; assign io_exit = id_reg_inst == 32'hC0000000;
endmodule endmodule
// VCS coverage exclude_file // VCS coverage exclude_file
module mem_512x32( module mem_512x32(
input [8:0] R0_addr, input [8:0] R0_addr,
input R0_en, input R0_en,
R0_clk, R0_clk,
output [31:0] R0_data, output [31:0] R0_data,
input [8:0] R1_addr, input [8:0] R1_addr,
input R1_en, input R1_en,
R1_clk, R1_clk,
output [31:0] R1_data, output [31:0] R1_data,
input [8:0] W0_addr, input [8:0] W0_addr,
input W0_en, input W0_en,
W0_clk, W0_clk,
input [31:0] W0_data input [31:0] W0_data
); );
reg [31:0] Memory[0:511]; reg [31:0] Memory[0:511];
reg _R0_en_d0; reg _R0_en_d0;
reg [8:0] _R0_addr_d0; reg [8:0] _R0_addr_d0;
always @(posedge R0_clk) begin always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en; _R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr; _R0_addr_d0 <= R0_addr;
end // always @(posedge) end // always @(posedge)
reg _R1_en_d0; reg _R1_en_d0;
reg [8:0] _R1_addr_d0; reg [8:0] _R1_addr_d0;
always @(posedge R1_clk) begin always @(posedge R1_clk) begin
_R1_en_d0 <= R1_en; _R1_en_d0 <= R1_en;
_R1_addr_d0 <= R1_addr; _R1_addr_d0 <= R1_addr;
end // always @(posedge) end // always @(posedge)
always @(posedge W0_clk) begin always @(posedge W0_clk) begin
if (W0_en & 1'h1) if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data; Memory[W0_addr] <= W0_data;
end // always @(posedge) end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_ `ifdef ENABLE_INITIAL_MEM_
initial initial
$readmemh("src/hex/mem.hex", Memory); $readmemh("src/hex/mem.hex", Memory);
`endif // ENABLE_INITIAL_MEM_ `endif // ENABLE_INITIAL_MEM_
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx; assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
endmodule endmodule
module Memory( module Memory(
input clock, input clock,
input [31:0] io_imem_addr, input [31:0] io_imem_addr,
output [31:0] io_imem_inst, output [31:0] io_imem_inst,
input [31:0] io_dmem_addr, input [31:0] io_dmem_addr,
output [31:0] io_dmem_rdata, output [31:0] io_dmem_rdata,
input io_dmem_wen, input io_dmem_wen,
input [31:0] io_dmem_wdata input [31:0] io_dmem_wdata
); );
mem_512x32 mem_ext ( mem_512x32 mem_ext (
.R0_addr (io_imem_addr[10:2]), .R0_addr (io_imem_addr[10:2]),
.R0_en (1'h1), .R0_en (1'h1),
.R0_clk (clock), .R0_clk (clock),
.R0_data (io_imem_inst), .R0_data (io_imem_inst),
.R1_addr (io_dmem_addr[10:2]), .R1_addr (io_dmem_addr[10:2]),
.R1_en (1'h1), .R1_en (1'h1),
.R1_clk (clock), .R1_clk (clock),
.R1_data (io_dmem_rdata), .R1_data (io_dmem_rdata),
.W0_addr (io_dmem_addr[10:2]), .W0_addr (io_dmem_addr[10:2]),
.W0_en (io_dmem_wen), .W0_en (io_dmem_wen),
.W0_clk (clock), .W0_clk (clock),
.W0_data (io_dmem_wdata) .W0_data (io_dmem_wdata)
); );
endmodule endmodule
module Top( module Top(
input clock, input clock,
reset, reset,
output io_exit output io_exit
); );
wire [31:0] _memory_io_imem_inst; wire [31:0] _memory_io_imem_inst;
wire [31:0] _memory_io_dmem_rdata; wire [31:0] _memory_io_dmem_rdata;
wire [31:0] _core_io_imem_addr; wire [31:0] _core_io_imem_addr;
wire [31:0] _core_io_dmem_addr; wire [31:0] _core_io_dmem_addr;
wire _core_io_dmem_wen; wire _core_io_dmem_wen;
wire [31:0] _core_io_dmem_wdata; wire [31:0] _core_io_dmem_wdata;
Core core ( Core core (
.clock (clock), .clock (clock),
.reset (reset), .reset (reset),
.io_imem_addr (_core_io_imem_addr), .io_imem_addr (_core_io_imem_addr),
.io_imem_inst (_memory_io_imem_inst), .io_imem_inst (_memory_io_imem_inst),
.io_dmem_addr (_core_io_dmem_addr), .io_dmem_addr (_core_io_dmem_addr),
.io_dmem_rdata (_memory_io_dmem_rdata), .io_dmem_rdata (_memory_io_dmem_rdata),
.io_dmem_wen (_core_io_dmem_wen), .io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata), .io_dmem_wdata (_core_io_dmem_wdata),
.io_exit (io_exit) .io_exit (io_exit)
); );
Memory memory ( Memory memory (
.clock (clock), .clock (clock),
.io_imem_addr (_core_io_imem_addr), .io_imem_addr (_core_io_imem_addr),
.io_imem_inst (_memory_io_imem_inst), .io_imem_inst (_memory_io_imem_inst),
.io_dmem_addr (_core_io_dmem_addr), .io_dmem_addr (_core_io_dmem_addr),
.io_dmem_rdata (_memory_io_dmem_rdata), .io_dmem_rdata (_memory_io_dmem_rdata),
.io_dmem_wen (_core_io_dmem_wen), .io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata) .io_dmem_wdata (_core_io_dmem_wdata)
); );
endmodule endmodule

67
display.sv Executable file
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@ -0,0 +1,67 @@
module DynamicDisplay(
input clock,
reset,
input [31:0] reg_result,
output [3:0] io_anodes,
output [6:0] io_segments
);
reg [6:0] digit_segments [0:9];
initial begin
digit_segments[0] = 7'b0000001;
digit_segments[1] = 7'b1001111;
digit_segments[2] = 7'b0010010;
digit_segments[3] = 7'b0000110;
digit_segments[4] = 7'b1001100;
digit_segments[5] = 7'b0100100;
digit_segments[6] = 7'b0100000;
digit_segments[7] = 7'b0001111;
digit_segments[8] = 7'b0000000;
digit_segments[9] = 7'b0000100;
end
reg [3:0] anode_select [0:3];
initial begin
anode_select[0] = 4'b1110;
anode_select[1] = 4'b1101;
anode_select[2] = 4'b1011;
anode_select[3] = 4'b0111;
end
// 扫描计数器和时钟分频
reg [15:0] clkDiv; // 分频计数器
reg [1:0] scanCounter; // 扫描计数器
wire clk1kHz = (clkDiv == 16'd50_000);
always @(posedge clock or posedge reset) begin
if (reset) begin
clkDiv <= 16'd0;
scanCounter <= 2'd0;
end
else begin
if (clk1kHz) begin
clkDiv <= 16'd0;
scanCounter <= scanCounter + 2'd1;
end
else begin
clkDiv <= clkDiv + 16'd1;
end
end
end
reg [3:0] digit_value;
always @(*) begin
case (scanCounter)
2'b11: digit_value = reg_result / 1000; // 千位
2'b10: digit_value = (reg_result / 100) % 10; // 百位
2'b01: digit_value = (reg_result / 10) % 10; // 十位
2'b00: digit_value = reg_result % 10; // 个位
default:
digit_value = 4'd0;
endcase
end
assign io_segments = digit_segments[digit_value];
assign io_anodes = anode_select[scanCounter];
endmodule

32
micore.xdc Executable file
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@ -0,0 +1,32 @@
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN V17 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property PACKAGE_PIN E19 [get_ports success_led]
set_property IOSTANDARD LVCMOS33 [get_ports success_led]
set_property PACKAGE_PIN U19 [get_ports fail_led]
set_property IOSTANDARD LVCMOS33 [get_ports fail_led]
set_property PACKAGE_PIN U2 [get_ports {io_anodes[0]}]
set_property PACKAGE_PIN U4 [get_ports {io_anodes[1]}]
set_property PACKAGE_PIN V4 [get_ports {io_anodes[2]}]
set_property PACKAGE_PIN W4 [get_ports {io_anodes[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[3]}]
set_property PACKAGE_PIN U7 [get_ports {io_segments[0]}]
set_property PACKAGE_PIN V5 [get_ports {io_segments[1]}]
set_property PACKAGE_PIN U5 [get_ports {io_segments[2]}]
set_property PACKAGE_PIN V8 [get_ports {io_segments[3]}]
set_property PACKAGE_PIN U8 [get_ports {io_segments[4]}]
set_property PACKAGE_PIN W6 [get_ports {io_segments[5]}]
set_property PACKAGE_PIN W7 [get_ports {io_segments[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[6]}]