Add constraint file and display module

Top.sv

@@ -34,6 +34,8 @@ module regfile_32x32(
     end // always @(posedge)
     assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
     assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
+
+    // DynamicDisplay show_reg()
 endmodule
 
 module Core(
@@ -365,6 +367,7 @@ module mem_512x32(
     initial
         $readmemh("src/hex/mem.hex", Memory);
 `endif // ENABLE_INITIAL_MEM_
+
     assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
     assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
 endmodule

display.sv

@@ -0,0 +1,67 @@
+module DynamicDisplay(
+        input        clock,
+        reset,
+        input  [31:0] reg_result,
+        output [3:0] io_anodes,
+        output [6:0] io_segments
+    );
+
+    reg [6:0] digit_segments [0:9];
+    initial begin
+        digit_segments[0] = 7'b0000001;
+        digit_segments[1] = 7'b1001111;
+        digit_segments[2] = 7'b0010010;
+        digit_segments[3] = 7'b0000110;
+        digit_segments[4] = 7'b1001100;
+        digit_segments[5] = 7'b0100100;
+        digit_segments[6] = 7'b0100000;
+        digit_segments[7] = 7'b0001111;
+        digit_segments[8] = 7'b0000000;
+        digit_segments[9] = 7'b0000100;
+    end
+
+    reg [3:0] anode_select [0:3];
+    initial begin
+        anode_select[0] = 4'b1110;
+        anode_select[1] = 4'b1101;
+        anode_select[2] = 4'b1011;
+        anode_select[3] = 4'b0111;
+    end
+
+    // 扫描计数器和时钟分频
+    reg [15:0] clkDiv;          // 分频计数器
+    reg [1:0]  scanCounter;     // 扫描计数器
+    wire       clk1kHz = (clkDiv == 16'd50_000);
+
+    always @(posedge clock or posedge reset) begin
+        if (reset) begin
+            clkDiv <= 16'd0;
+            scanCounter <= 2'd0;
+        end
+        else begin
+            if (clk1kHz) begin
+                clkDiv <= 16'd0;
+                scanCounter <= scanCounter + 2'd1;
+            end
+            else begin
+                clkDiv <= clkDiv + 16'd1;
+            end
+        end
+    end
+
+    reg [3:0] digit_value;
+    always @(*) begin
+        case (scanCounter)
+            2'b11: digit_value = reg_result / 1000;         // 千位
+            2'b10: digit_value = (reg_result / 100) % 10;  // 百位
+            2'b01: digit_value = (reg_result / 10) % 10;   // 十位
+            2'b00: digit_value = reg_result % 10;          // 个位
+            default:
+                digit_value = 4'd0;
+        endcase
+    end
+
+    assign io_segments = digit_segments[digit_value];
+    assign io_anodes = anode_select[scanCounter];
+
+endmodule

micore.xdc

@@ -0,0 +1,32 @@
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+set_property PACKAGE_PIN W5 [get_ports clk] 
+set_property IOSTANDARD LVCMOS33 [get_ports clk] 
+set_property PACKAGE_PIN V17 [get_ports reset] 
+set_property IOSTANDARD LVCMOS33 [get_ports reset] 
+set_property PACKAGE_PIN E19 [get_ports success_led] 
+set_property IOSTANDARD LVCMOS33 [get_ports success_led]
+set_property PACKAGE_PIN U19 [get_ports fail_led] 
+set_property IOSTANDARD LVCMOS33 [get_ports fail_led]
+set_property PACKAGE_PIN U2 [get_ports {io_anodes[0]}]
+set_property PACKAGE_PIN U4 [get_ports {io_anodes[1]}]
+set_property PACKAGE_PIN V4 [get_ports {io_anodes[2]}]
+set_property PACKAGE_PIN W4 [get_ports {io_anodes[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[3]}]
+
+set_property PACKAGE_PIN U7 [get_ports {io_segments[0]}]
+set_property PACKAGE_PIN V5 [get_ports {io_segments[1]}]
+set_property PACKAGE_PIN U5 [get_ports {io_segments[2]}]
+set_property PACKAGE_PIN V8 [get_ports {io_segments[3]}]
+set_property PACKAGE_PIN U8 [get_ports {io_segments[4]}]
+set_property PACKAGE_PIN W6 [get_ports {io_segments[5]}]
+set_property PACKAGE_PIN W7 [get_ports {io_segments[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[6]}]