gh0s7/micore
1
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

SystemVerilog Module Complete

Browse Source
This commit is contained in:
CGH0S7
2025-01-01 23:19:43 +08:00
parent 99703db0db
commit 7ae5ee8c39
21 changed files with 1749 additions and 704 deletions
Download Patch File Download Diff File Expand all files Collapse all files

171
Memory.sv
View File

@ -1,64 +1,98 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Company:
// Engineer:
//
// Create Date: 2024/12/28 11:28:52
// Design Name:
// Design Name:
// Module Name: Regfile
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
//////////////////////////////////////////////////////////////////////////////////
module mem_512x32(
input [8:0] R0_addr,
module mem_4096x8(
input [11:0] R0_addr,
input R0_en,
R0_clk,
output [31:0] R0_data,
input [8:0] R1_addr,
output [7:0] R0_data,
input [11:0] R1_addr,
input R1_en,
R1_clk,
output [31:0] R1_data,
input [8:0] W0_addr,
output [7:0] R1_data,
input [11:0] R2_addr,
input R2_en,
R2_clk,
output [7:0] R2_data,
input [11:0] R3_addr,
input R3_en,
R3_clk,
output [7:0] R3_data,
input [11:0] R4_addr,
input R4_en,
R4_clk,
output [7:0] R4_data,
input [11:0] R5_addr,
input R5_en,
R5_clk,
output [7:0] R5_data,
input [11:0] R6_addr,
input R6_en,
R6_clk,
output [7:0] R6_data,
input [11:0] R7_addr,
input R7_en,
R7_clk,
output [7:0] R7_data,
input [11:0] W0_addr,
input W0_en,
W0_clk,
input [31:0] W0_data
input [7:0] W0_data,
input [11:0] W1_addr,
input W1_en,
W1_clk,
input [7:0] W1_data,
input [11:0] W2_addr,
input W2_en,
W2_clk,
input [7:0] W2_data,
input [11:0] W3_addr,
input W3_en,
W3_clk,
input [7:0] W3_data
);
reg [31:0] Memory[0:511];
reg _R0_en_d0;
reg [8:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end // always @(posedge)
reg _R1_en_d0;
reg [8:0] _R1_addr_d0;
always @(posedge R1_clk) begin
_R1_en_d0 <= R1_en;
_R1_addr_d0 <= R1_addr;
end // always @(posedge)
reg [7:0] Memory[0:4095];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
if (W2_en & 1'h1)
Memory[W2_addr] <= W2_data;
if (W3_en & 1'h1)
Memory[W3_addr] <= W3_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
initial
$readmemh("src/hex/mem.hex", Memory);
`endif // ENABLE_INITIAL_MEM_
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
endmodule
module Memory(
@ -71,18 +105,69 @@ module Memory(
input [31:0] io_dmem_wdata
);
mem_512x32 mem_ext (
.R0_addr (io_imem_addr[10:2]),
wire [7:0] _mem_ext_R0_data;
wire [7:0] _mem_ext_R1_data;
wire [7:0] _mem_ext_R2_data;
wire [7:0] _mem_ext_R3_data;
wire [7:0] _mem_ext_R4_data;
wire [7:0] _mem_ext_R5_data;
wire [7:0] _mem_ext_R6_data;
wire [7:0] _mem_ext_R7_data;
wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
mem_4096x8 mem_ext (
.R0_addr (io_imem_addr[11:0]),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (io_imem_inst),
.R1_addr (io_dmem_addr[10:2]),
.R0_data (_mem_ext_R0_data),
.R1_addr (io_imem_addr[11:0] + 12'h1),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (io_dmem_rdata),
.W0_addr (io_dmem_addr[10:2]),
.R1_data (_mem_ext_R1_data),
.R2_addr (io_imem_addr[11:0] + 12'h2),
.R2_en (1'h1),
.R2_clk (clock),
.R2_data (_mem_ext_R2_data),
.R3_addr (io_imem_addr[11:0] + 12'h3),
.R3_en (1'h1),
.R3_clk (clock),
.R3_data (_mem_ext_R3_data),
.R4_addr (io_dmem_addr[11:0]),
.R4_en (1'h1),
.R4_clk (clock),
.R4_data (_mem_ext_R4_data),
.R5_addr (_io_dmem_rdata_T_6),
.R5_en (1'h1),
.R5_clk (clock),
.R5_data (_mem_ext_R5_data),
.R6_addr (_io_dmem_rdata_T_3),
.R6_en (1'h1),
.R6_clk (clock),
.R6_data (_mem_ext_R6_data),
.R7_addr (_io_dmem_rdata_T),
.R7_en (1'h1),
.R7_clk (clock),
.R7_data (_mem_ext_R7_data),
.W0_addr (_io_dmem_rdata_T),
.W0_en (io_dmem_wen),
.W0_clk (clock),
.W0_data (io_dmem_wdata)
.W0_data (io_dmem_wdata[31:24]),
.W1_addr (_io_dmem_rdata_T_3),
.W1_en (io_dmem_wen),
.W1_clk (clock),
.W1_data (io_dmem_wdata[23:16]),
.W2_addr (_io_dmem_rdata_T_6),
.W2_en (io_dmem_wen),
.W2_clk (clock),
.W2_data (io_dmem_wdata[15:8]),
.W3_addr (io_dmem_addr[11:0]),
.W3_en (io_dmem_wen),
.W3_clk (clock),
.W3_data (io_dmem_wdata[7:0])
);
assign io_imem_inst =
{_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
assign io_dmem_rdata =
{_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
endmodule