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SystemVerilog Module Complete

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CGH0S7
2025-01-01 23:19:43 +08:00
parent 99703db0db
commit 7ae5ee8c39
21 changed files with 1749 additions and 704 deletions
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44
Top.sv
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@ -1,31 +1,30 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Company:
// Engineer:
//
// Create Date: 2024/12/28 11:25:38
// Design Name:
// Design Name:
// Module Name: Core
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
//////////////////////////////////////////////////////////////////////////////////
module Top(
input clock,
reset,
output io_exit,
output [3:0] io_anodes, // 新增：七段显示器的阳极控制信号
output [6:0] io_segments // 新增：七段显示器的段控制信号
output [3:0] io_anodes,
output [6:0] io_segments
);
wire [31:0] _memory_io_imem_inst;
@ -34,7 +33,6 @@ module Top(
wire [31:0] _core_io_dmem_addr;
wire _core_io_dmem_wen;
wire [31:0] _core_io_dmem_wdata;
wire [31:0] _core_s0_value;
Core core (
.clock (clock),
.reset (reset),
@ -44,8 +42,9 @@ module Top(
.io_dmem_rdata (_memory_io_dmem_rdata),
.io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata),
.io_exit (io_exit),
.s0_value (_core_s0_value)
.io_anodes (io_anodes),
.io_segments (io_segments),
.io_exit (io_exit)
);
Memory memory (
.clock (clock),
@ -56,13 +55,4 @@ module Top(
.io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata)
);
// 实例化 DynamicDisplay 模块
DynamicDisplay display (
.clock (clock),
.reset (reset),
.reg_result (_core_s0_value), // 连接 $s0 的值
.io_anodes (io_anodes), // 连接七段显示器的阳极控制信号
.io_segments(io_segments) // 连接七段显示器的段控制信号
);
endmodule