SystemVerilog Module Complete

2025-01-01 23:19:43 +08:00
parent 99703db0db
commit 7ae5ee8c39
21 changed files with 1749 additions and 704 deletions
--- a/target/scala-2.13/-name-_2.13-0.1.0.jar
+++ b/target/scala-2.13/-name-_2.13-0.1.0.jar
--- a/target/scala-2.13/zinc/inc_compile_2.13.zip
+++ b/target/scala-2.13/zinc/inc_compile_2.13.zip
--- a/target/streams/compile/compileIncremental/_global/streams/out
+++ b/target/streams/compile/compileIncremental/_global/streams/out
--- a/target/streams/compile/exportedProductJars/_global/streams/export
+++ b/target/streams/compile/exportedProductJars/_global/streams/export
@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
+/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
--- a/target/streams/compile/incOptions/_global/streams/out
+++ b/target/streams/compile/incOptions/_global/streams/out
@ -1,2 +1,11 @@
 [0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak[0m
+[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
+[0m[[0m[0mdebug[0m] [0m[0m	Core$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	Core.class[0m
+[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
+[0m[[0m[0mdebug[0m] [0m[0m	Core$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	Core.class[0m
+[0m[[0m[0mdebug[0m] [0m[0mRegistering generated classes:[0m
+[0m[[0m[0mdebug[0m] [0m[0m	Core$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	Core.class[0m
 [0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak[0m
--- a/target/streams/compile/packageBin/_global/streams/inputs
+++ b/target/streams/compile/packageBin/_global/streams/inputs
@ -1 +1 @@
-160837087
+-18168398
--- a/target/streams/compile/packageBin/_global/streams/out
+++ b/target/streams/compile/packageBin/_global/streams/out
@ -1,73 +1,57 @@
-[0m[[0m[0mdebug[0m] [0m[0mPackaging /home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ...[0m
+[0m[[0m[0mdebug[0m] [0m[0mPackaging /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ...[0m
 [0m[[0m[0mdebug[0m] [0m[0mInput file mappings:[0m
-[0m[[0m[0mdebug[0m] [0m[0m	gcd[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd[0m
-[0m[[0m[0mdebug[0m] [0m[0m	gcd/GcdInputBundle.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdInputBundle.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	gcd/GcdOutputBundle.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdOutputBundle.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	gcd/DecoupledGcd.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/DecoupledGcd.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	gcd/GCD.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	gcd/GCD$.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	gcd/GCD$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	gcd/GCD$delayedInit$body.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$delayedInit$body.class[0m
 [0m[[0m[0mdebug[0m] [0m[0m	common[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common[0m
 [0m[[0m[0mdebug[0m] [0m[0m	common/Consts$.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts$.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class[0m
 [0m[[0m[0mdebug[0m] [0m[0m	common/Consts.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class[0m
 [0m[[0m[0mdebug[0m] [0m[0m	common/Instructions$.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions$.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class[0m
 [0m[[0m[0mdebug[0m] [0m[0m	common/Instructions.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class[0m
 [0m[[0m[0mdebug[0m] [0m[0m	micore[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore[0m
-[0m[[0m[0mdebug[0m] [0m[0m	micore/Core.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore[0m
 [0m[[0m[0mdebug[0m] [0m[0m	micore/Core$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	micore/TopOrigin.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	micore/TopOrigin$.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	micore/TopOrigin$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	micore/TopOrigin$delayedInit$body.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	micore/ImemPortIo.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/ImemPortIo.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	micore/Core.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class[0m
 [0m[[0m[0mdebug[0m] [0m[0m	micore/DmemPortIo.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/DmemPortIo.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	micore/Memory.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	micore/ImemPortIo.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class[0m
 [0m[[0m[0mdebug[0m] [0m[0m	micore/Memory$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	micore/Memory.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	micore/TopOrigin$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	micore/TopOrigin$.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	micore/TopOrigin$delayedInit$body.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	micore/TopOrigin.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class[0m
 [0m[[0m[0mdebug[0m] [0m[0m	sicore[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore[0m
-[0m[[0m[0mdebug[0m] [0m[0m	sicore/TopOrigin.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	sicore/TopOrigin$.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	sicore/TopOrigin$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	sicore/TopOrigin$delayedInit$body.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$delayedInit$body.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	sicore/Core.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Core.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore[0m
 [0m[[0m[0mdebug[0m] [0m[0m	sicore/Core$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Core$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	sicore/ImemPortIo.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/ImemPortIo.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Core$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	sicore/Core.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Core.class[0m
 [0m[[0m[0mdebug[0m] [0m[0m	sicore/DmemPortIo.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/DmemPortIo.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	sicore/Memory.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Memory.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/DmemPortIo.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	sicore/ImemPortIo.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/ImemPortIo.class[0m
 [0m[[0m[0mdebug[0m] [0m[0m	sicore/Memory$$anon$1.class[0m
-[0m[[0m[0mdebug[0m] [0m[0m	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Memory$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Memory$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	sicore/Memory.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Memory.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	sicore/TopOrigin$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$$anon$1.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	sicore/TopOrigin$.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	sicore/TopOrigin$delayedInit$body.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$delayedInit$body.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	sicore/TopOrigin.class[0m
+[0m[[0m[0mdebug[0m] [0m[0m	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin.class[0m
 [0m[[0m[0mdebug[0m] [0m[0mDone packaging.[0m
--- a/target/streams/compile/packageBin/_global/streams/output
+++ b/target/streams/compile/packageBin/_global/streams/output
@ -1 +1 @@
-1488086236
+-1359482768
--- a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export
+++ b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export
--- a/target/streams/runtime/exportedProductJars/_global/streams/export
+++ b/target/streams/runtime/exportedProductJars/_global/streams/export
@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
+/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
--- a/target/streams/runtime/fullClasspathAsJars/_global/streams/export
+++ b/target/streams/runtime/fullClasspathAsJars/_global/streams/export
--- a/target/streams/runtime/internalDependencyAsJars/_global/streams/export
+++ b/target/streams/runtime/internalDependencyAsJars/_global/streams/export
@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
+/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar