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Chisel code optimized

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CGH0S7
2024-12-27 23:35:23 +08:00
parent ec0fd8812f
commit 7d9846b4a6
49 changed files with 603 additions and 662 deletions
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1
.gitignore vendored
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@ -7,6 +7,7 @@
.scalafmt.conf .scalafmt.conf
*.code-workspace *.code-workspace
target target
.vscode
# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
hs_err_pid* hs_err_pid*

389
Top.sv
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@ -16,12 +16,24 @@ module regfile_32x32(
); );
reg [31:0] Memory[0:31]; reg [31:0] Memory[0:31];
reg _R0_en_d0;
reg [4:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end // always @(posedge)
reg _R1_en_d0;
reg [4:0] _R1_addr_d0;
always @(posedge R1_clk) begin
_R1_en_d0 <= R1_en;
_R1_addr_d0 <= R1_addr;
end // always @(posedge)
always @(posedge W0_clk) begin always @(posedge W0_clk) begin
if (W0_en & 1'h1) if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data; Memory[W0_addr] <= W0_data;
end // always @(posedge) end // always @(posedge)
assign R0_data = R0_en ? Memory[R0_addr] : 32'bx; assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 32'bx; assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
endmodule endmodule
module Core( module Core(
@ -36,8 +48,6 @@ module Core(
output io_exit output io_exit
); );
wire exe_jmp_flg;
wire exe_br_flg;
wire [31:0] _regfile_ext_R0_data; wire [31:0] _regfile_ext_R0_data;
wire [31:0] _regfile_ext_R1_data; wire [31:0] _regfile_ext_R1_data;
reg [31:0] id_reg_pc; reg [31:0] id_reg_pc;
@ -54,72 +64,40 @@ module Core(
reg [31:0] exe_reg_imm_b_sext; reg [31:0] exe_reg_imm_b_sext;
reg [31:0] mem_reg_pc; reg [31:0] mem_reg_pc;
reg [4:0] mem_reg_wb_addr; reg [4:0] mem_reg_wb_addr;
reg [31:0] mem_reg_alu_out;
reg [31:0] mem_reg_rs2_data; reg [31:0] mem_reg_rs2_data;
reg [1:0] mem_reg_mem_wen;
reg [1:0] mem_reg_rf_wen; reg [1:0] mem_reg_rf_wen;
reg [2:0] mem_reg_wb_sel; reg [2:0] mem_reg_wb_sel;
reg [31:0] mem_reg_alu_out; reg [1:0] mem_reg_mem_wen;
reg [4:0] wb_reg_wb_addr; reg [4:0] wb_reg_wb_addr;
reg [1:0] wb_reg_rf_wen; reg [1:0] wb_reg_rf_wen;
reg [31:0] wb_reg_wb_data; reg [31:0] wb_reg_wb_data;
reg [31:0] if_reg_pc; reg [31:0] if_reg_pc;
wire _id_inst_T = exe_br_flg | exe_jmp_flg;
wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
wire stall_flg =
_id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1; wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
assign exe_br_flg = wire exe_br_flg =
exe_reg_exe_fun == 5'hB exe_reg_exe_fun == 5'hC
? exe_reg_op1_data == exe_reg_op2_data ? exe_reg_op1_data != exe_reg_op2_data
: exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data; : exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data;
assign exe_jmp_flg = exe_reg_wb_sel == 3'h3; wire exe_jmp_flg = exe_reg_wb_sel == 3'h3;
wire [31:0] mem_wb_data =
mem_reg_wb_sel == 3'h2
? io_dmem_rdata
: mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
always @(posedge clock) begin always @(posedge clock) begin
if (reset) begin automatic logic _id_inst_T = exe_br_flg | exe_jmp_flg;
id_reg_pc <= 32'h0; automatic logic _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
id_reg_inst <= 32'h0; automatic logic stall_flg;
exe_reg_pc <= 32'h0; automatic logic [31:0] id_inst;
exe_reg_wb_addr <= 5'h0;
exe_reg_op1_data <= 32'h0;
exe_reg_op2_data <= 32'h0;
exe_reg_rs2_data <= 32'h0;
exe_reg_exe_fun <= 5'h0;
exe_reg_mem_wen <= 2'h0;
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
exe_reg_imm_b_sext <= 32'h0;
mem_reg_pc <= 32'h0;
mem_reg_wb_addr <= 5'h0;
mem_reg_rs2_data <= 32'h0;
mem_reg_mem_wen <= 2'h0;
mem_reg_rf_wen <= 2'h0;
mem_reg_wb_sel <= 3'h0;
mem_reg_alu_out <= 32'h0;
wb_reg_wb_addr <= 5'h0;
wb_reg_rf_wen <= 2'h0;
wb_reg_wb_data <= 32'h0;
if_reg_pc <= 32'h0;
end
else begin
automatic logic _id_rs2_data_T_2; automatic logic _id_rs2_data_T_2;
automatic logic [31:0] id_rs2_data; automatic logic _id_rs2_data_T;
automatic logic [16:0] _GEN = {id_inst[31:26], id_inst[10:0]}; automatic logic [31:0] _id_rs2_data_T_8;
automatic logic _csignals_T_5 = _GEN == 17'h20; automatic logic [16:0] _GEN;
automatic logic [19:0] _GEN_0 = {id_inst[31:28], id_inst[15:0]}; automatic logic _csignals_T_5;
automatic logic _csignals_T_7 = _GEN_0 == 20'h80000; automatic logic [19:0] _GEN_0;
automatic logic _csignals_T_7;
automatic logic _csignals_T_9; automatic logic _csignals_T_9;
automatic logic _csignals_T_11; automatic logic _csignals_T_11;
automatic logic _csignals_T_13; automatic logic _csignals_T_13;
automatic logic _csignals_T_15; automatic logic _csignals_T_15;
automatic logic _csignals_T_17; automatic logic _csignals_T_17;
automatic logic _csignals_T_19; automatic logic _csignals_T_19;
automatic logic [16:0] _GEN_1 = {id_inst[30:20], id_inst[5:0]}; automatic logic [16:0] _GEN_1;
automatic logic _csignals_T_21; automatic logic _csignals_T_21;
automatic logic _csignals_T_23; automatic logic _csignals_T_23;
automatic logic _csignals_T_25; automatic logic _csignals_T_25;
@ -132,26 +110,35 @@ module Core(
automatic logic _GEN_2; automatic logic _GEN_2;
automatic logic _GEN_3; automatic logic _GEN_3;
automatic logic [1:0] csignals_1; automatic logic [1:0] csignals_1;
automatic logic [2:0] _csignals_T_90;
automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]}; automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
automatic logic [62:0] _exe_alu_out_T_14 = automatic logic [62:0] _exe_alu_out_T_8 =
{31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0]; {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
automatic logic [31:0] exe_alu_out; automatic logic [31:0] exe_alu_out;
automatic logic [7:0][31:0] _GEN_5; stall_flg =
_id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
_id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1; _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
id_rs2_data = _id_rs2_data_T = id_reg_inst[20:16] == 5'h0;
id_inst[20:16] == 5'h0 _id_rs2_data_T_8 =
? 32'h0 id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
: id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2 ? mem_reg_alu_out
? mem_wb_data : id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
: id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
? wb_reg_wb_data ? wb_reg_wb_data
: _regfile_ext_R0_data; : _regfile_ext_R0_data;
_GEN = {id_inst[31:26], id_inst[10:0]};
_csignals_T_5 = _GEN == 17'h20;
_GEN_0 = {id_inst[31:28], id_inst[15:0]};
_csignals_T_7 = _GEN_0 == 20'h80000;
_csignals_T_9 = _GEN == 17'h22; _csignals_T_9 = _GEN == 17'h22;
_csignals_T_11 = _GEN == 17'h24; _csignals_T_11 = _GEN == 17'h24;
_csignals_T_13 = _GEN == 17'h25; _csignals_T_13 = _GEN == 17'h25;
_csignals_T_15 = _GEN == 17'h26; _csignals_T_15 = _GEN == 17'h26;
_csignals_T_17 = _GEN_0 == 20'hC0000; _csignals_T_17 = _GEN_0 == 20'hC0000;
_csignals_T_19 = _GEN_0 == 20'hD0000; _csignals_T_19 = _GEN_0 == 20'hD0000;
_GEN_1 = {id_inst[30:20], id_inst[5:0]};
_csignals_T_21 = _GEN_1 == 17'h0; _csignals_T_21 = _GEN_1 == 17'h0;
_csignals_T_23 = _GEN_1 == 17'h2; _csignals_T_23 = _GEN_1 == 17'h2;
_csignals_T_25 = _GEN_1 == 17'h3; _csignals_T_25 = _GEN_1 == 17'h3;
@ -168,62 +155,8 @@ module Core(
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
? 2'h0 ? 2'h0
: _csignals_T_33 ? 2'h1 : _csignals_T_35 ? 2'h0 : {_csignals_T_37, 1'h0}; : _csignals_T_33 ? 2'h1 : _csignals_T_35 ? 2'h0 : {_csignals_T_37, 1'h0};
exe_alu_out = _csignals_T_90 =
exe_reg_exe_fun == 5'h1 _csignals_T_5
? exe_reg_op1_data + exe_reg_op2_data
: exe_reg_exe_fun == 5'h2
? exe_reg_op1_data - exe_reg_op2_data
: exe_reg_exe_fun == 5'h3
? exe_reg_op1_data & exe_reg_op2_data
: exe_reg_exe_fun == 5'h4
? exe_reg_op1_data | exe_reg_op2_data
: exe_reg_exe_fun == 5'h5
? exe_reg_op1_data ^ exe_reg_op2_data
: exe_reg_exe_fun == 5'h6
? _exe_alu_out_T_14[31:0]
: exe_reg_exe_fun == 5'h7
? exe_reg_op1_data >> _GEN_4
: exe_reg_exe_fun == 5'h8
? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
: exe_reg_exe_fun == 5'h9
? {31'h0,
$signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
: exe_reg_exe_fun == 5'hE
? exe_reg_op1_data
: 32'h0;
if (~stall_flg)
id_reg_pc <= if_reg_pc;
if (_id_inst_T)
id_reg_inst <= 32'h0;
else if (~stall_flg)
id_reg_inst <= io_imem_inst;
exe_reg_pc <= id_reg_pc;
exe_reg_wb_addr <= id_inst[15:11];
if (csignals_1 == 2'h0) begin
if (id_inst[25:21] == 5'h0)
exe_reg_op1_data <= 32'h0;
else if (id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2)
exe_reg_op1_data <= mem_wb_data;
else if (id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5)
exe_reg_op1_data <= wb_reg_wb_data;
else
exe_reg_op1_data <= _regfile_ext_R1_data;
end
else if (csignals_1 == 2'h1)
exe_reg_op1_data <= id_reg_pc;
else
exe_reg_op1_data <= 32'h0;
_GEN_5 =
{{32'h0},
{32'h0},
{{id_inst[15:0], 16'h0}},
{{{4{id_inst[25]}}, id_inst[25:0], 2'h0}},
{{{16{id_inst[15]}}, id_inst[15:0]}},
{{{16{id_inst[15]}}, id_inst[15:0]}},
{id_rs2_data},
{32'h0}};
exe_reg_op2_data <=
_GEN_5[_csignals_T_5
? 3'h1 ? 3'h1
: _csignals_T_7 : _csignals_T_7
? 3'h2 ? 3'h2
@ -235,8 +168,61 @@ module Core(
? 3'h1 ? 3'h1
: _csignals_T_33 : _csignals_T_33
? 3'h4 ? 3'h4
: _csignals_T_35 ? 3'h0 : {_csignals_T_37, 2'h1}]; : _csignals_T_35 ? 3'h0 : {_csignals_T_37, 2'h1};
exe_reg_rs2_data <= id_rs2_data; exe_alu_out =
exe_reg_exe_fun == 5'hE
? exe_reg_op1_data
: exe_reg_exe_fun == 5'h9
? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
: exe_reg_exe_fun == 5'h8
? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
: exe_reg_exe_fun == 5'h7
? exe_reg_op1_data >> _GEN_4
: exe_reg_exe_fun == 5'h6
? _exe_alu_out_T_8[31:0]
: exe_reg_exe_fun == 5'h5
? exe_reg_op1_data ^ exe_reg_op2_data
: exe_reg_exe_fun == 5'h4
? exe_reg_op1_data | exe_reg_op2_data
: exe_reg_exe_fun == 5'h3
? exe_reg_op1_data & exe_reg_op2_data
: exe_reg_exe_fun == 5'h2
? exe_reg_op1_data - exe_reg_op2_data
: exe_reg_exe_fun == 5'h1
? exe_reg_op1_data + exe_reg_op2_data
: 32'h0;
if (~stall_flg)
id_reg_pc <= if_reg_pc;
if (_id_inst_T)
id_reg_inst <= 32'h0;
else if (~stall_flg)
id_reg_inst <= io_imem_inst;
exe_reg_pc <= id_reg_pc;
exe_reg_wb_addr <= id_reg_inst[15:11];
if (csignals_1 == 2'h0)
exe_reg_op1_data <=
id_reg_inst[25:21] == 5'h0
? 32'h0
: id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
? mem_reg_alu_out
: id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
? wb_reg_wb_data
: _regfile_ext_R1_data;
else if (csignals_1 == 2'h1)
exe_reg_op1_data <= id_reg_pc;
else
exe_reg_op1_data <= 32'h0;
if (_csignals_T_90 == 3'h5)
exe_reg_op2_data <= {id_inst[15:0], 16'h0};
else if (_csignals_T_90 == 3'h4)
exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
else if (_csignals_T_90 == 3'h3 | _csignals_T_90 == 3'h2)
exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
else if (_csignals_T_90 != 3'h1 | _id_rs2_data_T)
exe_reg_op2_data <= 32'h0;
else
exe_reg_op2_data <= _id_rs2_data_T_8;
exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8;
if (_csignals_T_5 | _csignals_T_7) if (_csignals_T_5 | _csignals_T_7)
exe_reg_exe_fun <= 5'h1; exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_9) else if (_csignals_T_9)
@ -295,28 +281,32 @@ module Core(
exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]}; exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
mem_reg_pc <= exe_reg_pc; mem_reg_pc <= exe_reg_pc;
mem_reg_wb_addr <= exe_reg_wb_addr; mem_reg_wb_addr <= exe_reg_wb_addr;
mem_reg_alu_out <= exe_alu_out;
mem_reg_rs2_data <= exe_reg_rs2_data; mem_reg_rs2_data <= exe_reg_rs2_data;
mem_reg_mem_wen <= exe_reg_mem_wen;
mem_reg_rf_wen <= exe_reg_rf_wen; mem_reg_rf_wen <= exe_reg_rf_wen;
mem_reg_wb_sel <= exe_reg_wb_sel; mem_reg_wb_sel <= exe_reg_wb_sel;
mem_reg_alu_out <= exe_alu_out; mem_reg_mem_wen <= exe_reg_mem_wen;
wb_reg_wb_addr <= mem_reg_wb_addr; wb_reg_wb_addr <= mem_reg_wb_addr;
wb_reg_rf_wen <= mem_reg_rf_wen; wb_reg_rf_wen <= mem_reg_rf_wen;
wb_reg_wb_data <= mem_wb_data; wb_reg_wb_data <=
if (exe_br_flg) mem_reg_wb_sel == 3'h3
? mem_reg_pc + 32'h4
: mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out;
if (reset)
if_reg_pc <= 32'h0;
else if (exe_br_flg)
if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext; if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
else if (exe_jmp_flg) else if (exe_jmp_flg)
if_reg_pc <= exe_alu_out; if_reg_pc <= exe_alu_out;
else if (~stall_flg) else if (~stall_flg)
if_reg_pc <= if_reg_pc + 32'h4; if_reg_pc <= if_reg_pc + 32'h4;
end
end // always @(posedge) end // always @(posedge)
regfile_32x32 regfile_ext ( regfile_32x32 regfile_ext (
.R0_addr (id_inst[20:16]), .R0_addr (id_reg_inst[20:16]),
.R0_en (1'h1), .R0_en (1'h1),
.R0_clk (clock), .R0_clk (clock),
.R0_data (_regfile_ext_R0_data), .R0_data (_regfile_ext_R0_data),
.R1_addr (id_inst[25:21]), .R1_addr (id_reg_inst[25:21]),
.R1_en (1'h1), .R1_en (1'h1),
.R1_clk (clock), .R1_clk (clock),
.R1_data (_regfile_ext_R1_data), .R1_data (_regfile_ext_R1_data),
@ -333,80 +323,44 @@ module Core(
endmodule endmodule
// VCS coverage exclude_file // VCS coverage exclude_file
module mem_8192x8( module mem_512x32(
input [12:0] R0_addr, input [8:0] R0_addr,
input R0_en, input R0_en,
R0_clk, R0_clk,
output [7:0] R0_data, output [31:0] R0_data,
input [12:0] R1_addr, input [8:0] R1_addr,
input R1_en, input R1_en,
R1_clk, R1_clk,
output [7:0] R1_data, output [31:0] R1_data,
input [12:0] R2_addr, input [8:0] W0_addr,
input R2_en,
R2_clk,
output [7:0] R2_data,
input [12:0] R3_addr,
input R3_en,
R3_clk,
output [7:0] R3_data,
input [12:0] R4_addr,
input R4_en,
R4_clk,
output [7:0] R4_data,
input [12:0] R5_addr,
input R5_en,
R5_clk,
output [7:0] R5_data,
input [12:0] R6_addr,
input R6_en,
R6_clk,
output [7:0] R6_data,
input [12:0] R7_addr,
input R7_en,
R7_clk,
output [7:0] R7_data,
input [12:0] W0_addr,
input W0_en, input W0_en,
W0_clk, W0_clk,
input [7:0] W0_data, input [31:0] W0_data
input [12:0] W1_addr,
input W1_en,
W1_clk,
input [7:0] W1_data,
input [12:0] W2_addr,
input W2_en,
W2_clk,
input [7:0] W2_data,
input [12:0] W3_addr,
input W3_en,
W3_clk,
input [7:0] W3_data
); );
reg [7:0] Memory[0:8191]; reg [31:0] Memory[0:511];
reg _R0_en_d0;
reg [8:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end // always @(posedge)
reg _R1_en_d0;
reg [8:0] _R1_addr_d0;
always @(posedge R1_clk) begin
_R1_en_d0 <= R1_en;
_R1_addr_d0 <= R1_addr;
end // always @(posedge)
always @(posedge W0_clk) begin always @(posedge W0_clk) begin
if (W0_en & 1'h1) if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data; Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
if (W2_en & 1'h1)
Memory[W2_addr] <= W2_data;
if (W3_en & 1'h1)
Memory[W3_addr] <= W3_data;
end // always @(posedge) end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_ `ifdef ENABLE_INITIAL_MEM_
initial initial
$readmemh("src/hex/mem.hex", Memory); $readmemh("src/hex/mem.hex", Memory);
`endif // ENABLE_INITIAL_MEM_ `endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 8'bx; assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 8'bx; assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
endmodule endmodule
module Memory( module Memory(
@ -419,71 +373,20 @@ module Memory(
input [31:0] io_dmem_wdata input [31:0] io_dmem_wdata
); );
wire [7:0] _mem_ext_R0_data; mem_512x32 mem_ext (
wire [7:0] _mem_ext_R1_data; .R0_addr (io_imem_addr[10:2]),
wire [7:0] _mem_ext_R2_data;
wire [7:0] _mem_ext_R3_data;
wire [7:0] _mem_ext_R4_data;
wire [7:0] _mem_ext_R5_data;
wire [7:0] _mem_ext_R6_data;
wire [7:0] _mem_ext_R7_data;
wire [12:0] _io_dmem_rdata_T_1 = io_dmem_addr[12:0] + 13'h1;
wire [12:0] _io_dmem_rdata_T_4 = io_dmem_addr[12:0] + 13'h2;
wire [12:0] _io_dmem_rdata_T_7 = io_dmem_addr[12:0] + 13'h3;
mem_8192x8 mem_ext (
.R0_addr (io_imem_addr[12:0] + 13'h3),
.R0_en (1'h1), .R0_en (1'h1),
.R0_clk (clock), .R0_clk (clock),
.R0_data (_mem_ext_R0_data), .R0_data (io_imem_inst),
.R1_addr (io_imem_addr[12:0] + 13'h2), .R1_addr (io_dmem_addr[10:2]),
.R1_en (1'h1), .R1_en (1'h1),
.R1_clk (clock), .R1_clk (clock),
.R1_data (_mem_ext_R1_data), .R1_data (io_dmem_rdata),
.R2_addr (io_imem_addr[12:0] + 13'h1), .W0_addr (io_dmem_addr[10:2]),
.R2_en (1'h1),
.R2_clk (clock),
.R2_data (_mem_ext_R2_data),
.R3_addr (io_imem_addr[12:0]),
.R3_en (1'h1),
.R3_clk (clock),
.R3_data (_mem_ext_R3_data),
.R4_addr (_io_dmem_rdata_T_7),
.R4_en (1'h1),
.R4_clk (clock),
.R4_data (_mem_ext_R4_data),
.R5_addr (_io_dmem_rdata_T_4),
.R5_en (1'h1),
.R5_clk (clock),
.R5_data (_mem_ext_R5_data),
.R6_addr (_io_dmem_rdata_T_1),
.R6_en (1'h1),
.R6_clk (clock),
.R6_data (_mem_ext_R6_data),
.R7_addr (io_dmem_addr[12:0]),
.R7_en (1'h1),
.R7_clk (clock),
.R7_data (_mem_ext_R7_data),
.W0_addr (_io_dmem_rdata_T_7),
.W0_en (io_dmem_wen), .W0_en (io_dmem_wen),
.W0_clk (clock), .W0_clk (clock),
.W0_data (io_dmem_wdata[7:0]), .W0_data (io_dmem_wdata)
.W1_addr (_io_dmem_rdata_T_4),
.W1_en (io_dmem_wen),
.W1_clk (clock),
.W1_data (io_dmem_wdata[15:8]),
.W2_addr (_io_dmem_rdata_T_1),
.W2_en (io_dmem_wen),
.W2_clk (clock),
.W2_data (io_dmem_wdata[23:16]),
.W3_addr (io_dmem_addr[12:0]),
.W3_en (io_dmem_wen),
.W3_clk (clock),
.W3_data (io_dmem_wdata[31:24])
); );
assign io_imem_inst =
{_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
assign io_dmem_rdata =
{_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
endmodule endmodule
module Top( module Top(

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@ -1 +1 @@
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}} {"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}

11
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@ -1,3 +1,8 @@
[debug] not up to date. inChanged = true, force = false [warn] sbt-bloop_2.12_1.0-2.0.6.jar no longer exists at /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar
[debug] Updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/project/"), "micore-build-build-build")... [debug] not up to date. inChanged = false, force = false
[debug] Done updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/project/"), "micore-build-build-build") [debug] Updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/project/"), "micore-build-build-build")...
[info] Updating 
[info] Resolved dependencies
[info] Fetching artifacts of 
[info] Fetched artifacts of 
[debug] Done updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/project/"), "micore-build-build-build")

2
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@ -1 +1 @@
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] ["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

2
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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

6
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@ -1,5 +1,5 @@
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files: [debug] About to delete class files:
[debug] We backup class files: [debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak

2
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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

2
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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

2
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@ -1 +1 @@
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}} {"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}

9
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@ -1,3 +1,6 @@
[debug] not up to date. inChanged = true, force = false [warn] sbt-bloop_2.12_1.0-2.0.6-sources.jar no longer exists at /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6-sources.jar
[debug] Updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")... [debug] not up to date. inChanged = false, force = false
[debug] Done updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build") [debug] Updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/"), "micore-build-build")...
[info] Fetching artifacts of 
[info] Fetched artifacts of 
[debug] Done updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/"), "micore-build-build")

2
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@ -1 +1 @@
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] ["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

2
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@ -1,4 +1,4 @@
[debug] [micore-build-build] Classpath dependencies List() [debug] [micore-build-build] Classpath dependencies List()
[debug] [micore-build-build] Dependencies from configurations List() [debug] [micore-build-build] Dependencies from configurations List()
[debug] Bloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json' [debug] Bloop wrote the configuration of project 'micore-build-build' to '/home/gh0s7/nfs/project/micore/project/project/.bloop/micore-build-build.json'
[success] Generated .bloop/micore-build-build.json [success] Generated .bloop/micore-build-build.json

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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes

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@ -1,5 +1,5 @@
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files: [debug] About to delete class files:
[debug] We backup class files: [debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak

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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes

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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes

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@ -1 +1 @@
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}} {"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}

2
project/target/streams/compile/_global/_global/compileOutputs/previous
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@ -1 +1 @@
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] ["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

2
project/target/streams/compile/bloopGenerate/_global/streams/out
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@ -1,4 +1,4 @@
[debug] [micore-build] Classpath dependencies List() [debug] [micore-build] Classpath dependencies List()
[debug] [micore-build] Dependencies from configurations List() [debug] [micore-build] Dependencies from configurations List()
[debug] Bloop wrote the configuration of project 'micore-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/.bloop/micore-build.json' [debug] Bloop wrote the configuration of project 'micore-build' to '/home/gh0s7/nfs/project/micore/project/.bloop/micore-build.json'
[success] Generated .bloop/micore-build.json [success] Generated .bloop/micore-build.json

2
project/target/streams/compile/exportedProducts/_global/streams/export
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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes

6
project/target/streams/compile/incOptions/_global/streams/out
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@ -1,5 +1,5 @@
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files: [debug] About to delete class files:
[debug] We backup class files: [debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak

2
project/target/streams/runtime/dependencyClasspath/_global/streams/export
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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

2
project/target/streams/runtime/exportedProducts/_global/streams/export
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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes

2
project/target/streams/runtime/fullClasspath/_global/streams/export
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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

2
project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes

305
src/main/scala/micore/Core.scala
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@ -4,7 +4,6 @@ import chisel3._
import chisel3.util._ import chisel3.util._
import common.Consts._ import common.Consts._
import common.Instructions._ import common.Instructions._
import os.list
class Core extends Module { class Core extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
@ -13,57 +12,57 @@ class Core extends Module {
val exit = Output(Bool()) val exit = Output(Bool())
}) })
val regfile = Mem(32, UInt(WORD_LEN.W)) // Block RAM for data memory
val regfile = SyncReadMem(32, UInt(WORD_LEN.W))
// ********* Pipeline Registers ********* // ********* Pipeline Registers *********
// IF/ID state val id_reg = Reg(new Bundle {
val id_reg_pc = RegInit(0.U(WORD_LEN.W)) val pc = UInt(WORD_LEN.W)
val id_reg_inst = RegInit(0.U(WORD_LEN.W)) val inst = UInt(WORD_LEN.W)
})
// ID/EX state val exe_reg = Reg(new Bundle {
val exe_reg_pc = RegInit(0.U(WORD_LEN.W)) val pc = UInt(WORD_LEN.W)
val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) val wb_addr = UInt(ADDR_LEN.W)
val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W)) val op1_data = UInt(WORD_LEN.W)
val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W)) val op2_data = UInt(WORD_LEN.W)
val exe_reg_rs2_data = RegInit(0.U(WORD_LEN.W)) val rs2_data = UInt(WORD_LEN.W)
val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W)) val exe_fun = UInt(EXE_FUN_LEN.W)
val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) val mem_wen = UInt(MEN_LEN.W)
val exe_reg_rf_wen = RegInit(0.U(REN_LEN.W)) val rf_wen = UInt(REN_LEN.W)
val exe_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W)) val wb_sel = UInt(WB_SEL_LEN.W)
val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W)) val imm_b_sext = UInt(WORD_LEN.W)
val exe_reg_imm_s_sext = RegInit(0.U(WORD_LEN.W)) })
val exe_reg_imm_b_sext = RegInit(0.U(WORD_LEN.W))
val exe_reg_imm_u_shifted = RegInit(0.U(WORD_LEN.W))
// EX/MEM state val mem_reg = Reg(new Bundle {
val mem_reg_pc = RegInit(0.U(WORD_LEN.W)) val pc = UInt(WORD_LEN.W)
val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) val wb_addr = UInt(ADDR_LEN.W)
val mem_reg_op1_data = RegInit(0.U(WORD_LEN.W)) val alu_out = UInt(WORD_LEN.W)
val mem_reg_rs2_data = RegInit(0.U(WORD_LEN.W)) val rs2_data = UInt(WORD_LEN.W)
val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) val rf_wen = UInt(REN_LEN.W)
val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W)) val wb_sel = UInt(WB_SEL_LEN.W)
val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W)) val mem_wen = UInt(MEN_LEN.W)
val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W)) })
// MEM/WB state val wb_reg = Reg(new Bundle {
val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) val wb_addr = UInt(ADDR_LEN.W)
val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W)) val rf_wen = UInt(REN_LEN.W)
val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W)) val wb_data = UInt(WORD_LEN.W)
})
// ********* Instruction Fetch (IF) Stage ********* // ********* Instruction Fetch (IF) Stage *********
val if_reg_pc = RegInit(START_ADDR) val if_reg_pc = RegInit(START_ADDR)
io.imem.addr := if_reg_pc io.imem.addr := if_reg_pc
val if_inst = io.imem.inst val if_inst = io.imem.inst
val stall_flg = Wire(Bool()) // 停顿标志 val stall_flg = Wire(Bool())
val exe_br_flg = Wire(Bool()) // 跳转标志 val exe_br_flg = Wire(Bool())
val exe_br_target = Wire(UInt(WORD_LEN.W)) // 跳转目标地址 val exe_br_target = Wire(UInt(WORD_LEN.W))
val exe_jmp_flg = Wire(Bool()) // 跳转标志 val exe_jmp_flg = Wire(Bool())
val exe_alu_out = Wire(UInt(WORD_LEN.W)) // ALU输出 val exe_alu_out = Wire(UInt(WORD_LEN.W))
val if_pc_plus4 = if_reg_pc + 4.U(WORD_LEN.W) val if_pc_plus4 = if_reg_pc + 4.U(WORD_LEN.W)
val if_pc_next = val if_pc_next = MuxCase(
MuxCase(
if_pc_plus4, if_pc_plus4,
Seq( Seq(
exe_br_flg -> exe_br_target, exe_br_flg -> exe_br_target,
@ -74,63 +73,62 @@ class Core extends Module {
if_reg_pc := if_pc_next if_reg_pc := if_pc_next
// ********* IF/ID Stage ********* // ********* IF/ID Stage *********
id_reg_pc := Mux(stall_flg, id_reg_pc, if_reg_pc) id_reg.pc := Mux(stall_flg, id_reg.pc, if_reg_pc)
id_reg_inst := MuxCase( id_reg.inst := MuxCase(
if_inst, if_inst,
Seq( Seq(
(exe_br_flg || exe_jmp_flg) -> BUBBLE, (exe_br_flg || exe_jmp_flg) -> BUBBLE,
stall_flg -> id_reg_inst stall_flg -> id_reg.inst
) )
) )
// ********* Decode (ID) Stage ********* // ********* Decode (ID) Stage *********
val id_rs1_addr_b = id_reg_inst(25, 21) val id_rs1_addr = id_reg.inst(25, 21)
val id_rs2_addr_b = id_reg_inst(20, 16) val id_rs2_addr = id_reg.inst(20, 16)
val id_wb_addr = id_reg.inst(15, 11)
// 与EX数据冒险 // Data Hazard
val id_rs1_data_hazard = val id_rs1_data_hazard =
(exe_reg_rf_wen === REN_S) && (id_rs1_addr_b =/= 0.U) && (id_rs1_addr_b === exe_reg_wb_addr) (exe_reg.rf_wen === REN_S) && (id_rs1_addr =/= 0.U) && (id_rs1_addr === exe_reg.wb_addr)
val id_rs2_data_hazard = val id_rs2_data_hazard =
(exe_reg_rf_wen === REN_S) && (id_rs2_addr_b =/= 0.U) && (id_rs2_addr_b === exe_reg_wb_addr) (exe_reg.rf_wen === REN_S) && (id_rs2_addr =/= 0.U) && (id_rs2_addr === exe_reg.wb_addr)
stall_flg := (id_rs1_data_hazard || id_rs2_data_hazard) stall_flg := (id_rs1_data_hazard || id_rs2_data_hazard)
val id_inst = val id_inst = Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg.inst)
Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst)
val id_rs1_addr = id_inst(25, 21) val id_rs1_data = Mux(
val id_rs2_addr = id_inst(20, 16) id_rs1_addr === 0.U,
val id_wb_addr = id_inst(15, 11) 0.U(WORD_LEN.W),
val mem_wb_data = Wire(UInt(WORD_LEN.W)) Mux(
val id_rs1_data = MuxCase( (id_rs1_addr === mem_reg.wb_addr) && (mem_reg.rf_wen === REN_S),
regfile(id_rs1_addr), mem_reg.alu_out,
Seq( Mux(
(id_rs1_addr === 0.U) -> 0.U(WORD_LEN.W), (id_rs1_addr === wb_reg.wb_addr) && (wb_reg.rf_wen === REN_S),
((id_rs1_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通 wb_reg.wb_data,
((id_rs1_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通 regfile(id_rs1_addr)
) )
) )
val id_rs2_data = MuxCase( )
regfile(id_rs2_addr), val id_rs2_data = Mux(
Seq( id_rs2_addr === 0.U,
(id_rs2_addr === 0.U) -> 0.U(WORD_LEN.W), 0.U(WORD_LEN.W),
((id_rs2_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通 Mux(
((id_rs2_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通 (id_rs2_addr === mem_reg.wb_addr) && (mem_reg.rf_wen === REN_S),
mem_reg.alu_out,
Mux(
(id_rs2_addr === wb_reg.wb_addr) && (wb_reg.rf_wen === REN_S),
wb_reg.wb_data,
regfile(id_rs2_addr)
)
) )
) )
val id_imm_i = id_inst(15, 0) // 立即数扩展
val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i) val id_imm_i_sext = Cat(Fill(16, id_inst(15)), id_inst(15, 0))
val id_imm_s = id_inst(15, 0) val id_imm_b_sext = Cat(Fill(16, id_inst(15)), id_inst(15, 0))
val id_imm_s_sext = Cat(Fill(16, id_imm_s(15)), id_imm_s)
val id_imm_b = id_inst(15, 0)
val id_imm_b_sext = Cat(Fill(16, id_imm_b(15)), id_imm_b)
val id_imm_j = id_inst(25, 0)
val id_imm_j_sext = Cat(Fill(4, id_imm_j(25)), id_imm_j, 0.U(2.W))
val id_imm_u = id_inst(15, 0)
val id_imm_u_shifted = Cat(id_imm_u, Fill(16, 0.U(1.W)))
val csignals = // 控制信号解码
ListLookup( val csignals = ListLookup(
id_inst, id_inst,
List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
Array( Array(
@ -156,110 +154,103 @@ class Core extends Module {
) )
) )
val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil = val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil = csignals
csignals
val id_op1_data = MuxCase( val id_op1_data = Mux(
0.U(WORD_LEN.W), id_op1_sel === OP1_RS1,
Seq( id_rs1_data,
(id_op1_sel === OP1_RS1) -> id_rs1_data, Mux(id_op1_sel === OP1_PC, id_reg.pc, 0.U(WORD_LEN.W))
(id_op1_sel === OP1_PC) -> id_reg_pc
) )
) val id_op2_data = MuxLookup(
val id_op2_data = MuxCase( id_op2_sel,
0.U(WORD_LEN.W), 0.U(WORD_LEN.W)
)(
Seq( Seq(
(id_op2_sel === OP2_RS2) -> id_rs2_data, OP2_RS2 -> id_rs2_data,
(id_op2_sel === OP2_IMI) -> id_imm_i_sext, OP2_IMI -> id_imm_i_sext,
(id_op2_sel === OP2_IMS) -> id_imm_s_sext, OP2_IMS -> id_imm_i_sext,
(id_op2_sel === OP2_IMJ) -> id_imm_j_sext, OP2_IMJ -> Cat(Fill(4, id_inst(25)), id_inst(25, 0), 0.U(2.W)),
(id_op2_sel === OP2_IMU) -> id_imm_u_shifted OP2_IMU -> Cat(id_inst(15, 0), Fill(16, 0.U))
) )
) )
// ********* Decode/Execute (ID/EX) Stage ********* // ********* Decode/Execute (ID/EX) Stage *********
exe_reg_pc := id_reg_pc exe_reg.pc := id_reg.pc
exe_reg_op1_data := id_op1_data exe_reg.op1_data := id_op1_data
exe_reg_op2_data := id_op2_data exe_reg.op2_data := id_op2_data
exe_reg_rs2_data := id_rs2_data exe_reg.rs2_data := id_rs2_data
exe_reg_wb_addr := id_wb_addr exe_reg.wb_addr := id_wb_addr
exe_reg_wb_sel := id_wb_sel exe_reg.wb_sel := id_wb_sel
exe_reg_mem_wen := id_mem_wen exe_reg.mem_wen := id_mem_wen
exe_reg_rf_wen := id_rf_wen exe_reg.rf_wen := id_rf_wen
exe_reg_imm_b_sext := id_imm_b_sext exe_reg.imm_b_sext := id_imm_b_sext
exe_reg_imm_i_sext := id_imm_i_sext exe_reg.exe_fun := id_exe_fun
exe_reg_imm_s_sext := id_imm_s_sext
exe_reg_imm_u_shifted := id_imm_u_shifted
exe_reg_exe_fun := id_exe_fun
// ********* Execute (EX) Stage ********* // ********* Execute (EX) Stage *********
exe_alu_out := MuxCase( exe_alu_out := MuxLookup(
0.U(WORD_LEN.W), exe_reg.exe_fun,
0.U(WORD_LEN.W)
)(
Seq( Seq(
(exe_reg_exe_fun === ALU_ADD) -> (exe_reg_op1_data + exe_reg_op2_data), ALU_ADD -> (exe_reg.op1_data + exe_reg.op2_data),
(exe_reg_exe_fun === ALU_SUB) -> (exe_reg_op1_data - exe_reg_op2_data), ALU_SUB -> (exe_reg.op1_data - exe_reg.op2_data),
(exe_reg_exe_fun === ALU_AND) -> (exe_reg_op1_data & exe_reg_op2_data), ALU_AND -> (exe_reg.op1_data & exe_reg.op2_data),
(exe_reg_exe_fun === ALU_OR) -> (exe_reg_op1_data | exe_reg_op2_data), ALU_OR -> (exe_reg.op1_data | exe_reg.op2_data),
(exe_reg_exe_fun === ALU_XOR) -> (exe_reg_op1_data ^ exe_reg_op2_data), ALU_XOR -> (exe_reg.op1_data ^ exe_reg.op2_data),
(exe_reg_exe_fun === ALU_SLL) -> (exe_reg_op1_data << exe_reg_op2_data( ALU_SLL -> (exe_reg.op1_data << exe_reg.op2_data(4, 0))(31, 0),
4, ALU_SRL -> (exe_reg.op1_data >> exe_reg.op2_data(4, 0)).asUInt,
0 ALU_SRA -> (exe_reg.op1_data.asSInt >> exe_reg.op2_data(4, 0)).asUInt,
))(31, 0), ALU_SLT -> (exe_reg.op1_data.asSInt < exe_reg.op2_data.asSInt).asUInt,
(exe_reg_exe_fun === ALU_SRL) -> (exe_reg_op1_data >> exe_reg_op2_data( ALU_COPY1 -> exe_reg.op1_data
4,
0
)).asUInt,
(exe_reg_exe_fun === ALU_SRA) -> (exe_reg_op1_data.asSInt >> exe_reg_op2_data(
4,
0
)).asUInt,
(exe_reg_exe_fun === ALU_SLT) -> (exe_reg_op1_data.asSInt < exe_reg_op2_data.asSInt).asUInt,
(exe_reg_exe_fun === ALU_COPY1) -> exe_reg_op1_data
) )
) )
exe_br_flg := MuxCase( exe_br_flg := MuxLookup(
false.B, exe_reg.exe_fun,
false.B
)(
Seq( Seq(
(exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data), BR_BEQ -> (exe_reg.op1_data === exe_reg.op2_data),
(exe_reg_exe_fun === BR_BNE) -> (exe_reg_op1_data =/= exe_reg_op2_data) BR_BNE -> (exe_reg.op1_data =/= exe_reg.op2_data)
) )
) )
exe_br_target := exe_reg_pc + exe_reg_imm_b_sext exe_br_target := exe_reg.pc + exe_reg.imm_b_sext
exe_jmp_flg := (exe_reg.wb_sel === WB_PC)
exe_jmp_flg := (exe_reg_wb_sel === WB_PC) // ********* Execute/Memory (EX/MEM) Stage *********
mem_reg.pc := exe_reg.pc
mem_reg.wb_addr := exe_reg.wb_addr
mem_reg.alu_out := exe_alu_out
mem_reg.rs2_data := exe_reg.rs2_data
mem_reg.rf_wen := exe_reg.rf_wen
mem_reg.wb_sel := exe_reg.wb_sel
mem_reg.mem_wen := exe_reg.mem_wen
// ********** Execute/Memory (EX/MEM) Stage *********** // ********* Memory (MEM) Stage *********
mem_reg_pc := exe_reg_pc io.dmem.addr := mem_reg.alu_out
mem_reg_op1_data := exe_reg_op1_data io.dmem.wen := mem_reg.mem_wen
mem_reg_rs2_data := exe_reg_rs2_data io.dmem.wdata := mem_reg.rs2_data
mem_reg_wb_addr := exe_reg_wb_addr
mem_reg_alu_out := exe_alu_out
mem_reg_rf_wen := exe_reg_rf_wen
mem_reg_wb_sel := exe_reg_wb_sel
mem_reg_mem_wen := exe_reg_mem_wen
// ********* Memory (MEM) Stage *********** val mem_wb_data = MuxLookup(
io.dmem.addr := mem_reg_alu_out mem_reg.wb_sel,
io.dmem.wen := mem_reg_mem_wen mem_reg.alu_out
io.dmem.wdata := mem_reg_rs2_data )(
mem_wb_data := MuxCase(
mem_reg_alu_out,
Seq( Seq(
(mem_reg_wb_sel === WB_MEM) -> io.dmem.rdata, WB_MEM -> io.dmem.rdata,
(mem_reg_wb_sel === WB_PC) -> (mem_reg_pc + 4.U(WORD_LEN.W)) WB_PC -> (mem_reg.pc + 4.U(WORD_LEN.W))
) )
) )
// ********** Memory/Write Back (MEM/WB) Stage ***********
wb_reg_wb_data := mem_wb_data // ********* Memory/Write Back (MEM/WB) Stage *********
wb_reg_rf_wen := mem_reg_rf_wen wb_reg.wb_addr := mem_reg.wb_addr
wb_reg_wb_addr := mem_reg_wb_addr wb_reg.rf_wen := mem_reg.rf_wen
wb_reg.wb_data := mem_wb_data
// ********* Write Back (WB) Stage ********* // ********* Write Back (WB) Stage *********
when(wb_reg_rf_wen === REN_S) { regfile(wb_reg_wb_addr) := wb_reg_wb_data } when(wb_reg.rf_wen === REN_S) {
regfile(wb_reg.wb_addr) := wb_reg.wb_data
io.exit := (id_reg_inst === UNIMP) }
io.exit := (id_reg.inst === UNIMP)
} }

22
src/main/scala/micore/Memory.scala
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@ -23,28 +23,16 @@ class Memory extends Module {
val dmem = new DmemPortIo val dmem = new DmemPortIo
}) })
val mem = Mem(8192, UInt(8.W)) // val mem = Mem(8192, UInt(8.W))
val mem = SyncReadMem(512, UInt(WORD_LEN.W))
loadMemoryFromFileInline(mem, "src/hex/mem.hex") loadMemoryFromFileInline(mem, "src/hex/mem.hex")
io.imem.inst := Cat( io.imem.inst := mem.read(io.imem.addr >> 2)
mem(io.imem.addr),
mem(io.imem.addr + 1.U(WORD_LEN.W)),
mem(io.imem.addr + 2.U(WORD_LEN.W)),
mem(io.imem.addr + 3.U(WORD_LEN.W))
)
io.dmem.rdata := Cat( io.dmem.rdata := mem.read(io.dmem.addr >> 2)
mem(io.dmem.addr),
mem(io.dmem.addr + 1.U(WORD_LEN.W)),
mem(io.dmem.addr + 2.U(WORD_LEN.W)),
mem(io.dmem.addr + 3.U(WORD_LEN.W))
)
when(io.dmem.wen) { when(io.dmem.wen) {
mem(io.dmem.addr) := io.dmem.wdata(31, 24) mem.write(io.dmem.addr >> 2, io.dmem.wdata)
mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(23, 16)
mem(io.dmem.addr + 2.U(WORD_LEN.W)) := io.dmem.wdata(15, 8)
mem(io.dmem.addr + 3.U(WORD_LEN.W)) := io.dmem.wdata(7, 0)
} }
} }

7
src/main/scala/micore/Top.scala
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@ -23,6 +23,11 @@ class Top extends Module {
object Top extends App { object Top extends App {
ChiselStage.emitSystemVerilogFile( ChiselStage.emitSystemVerilogFile(
new Top, new Top,
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") firtoolOpts = Array(
"--disable-all-randomization",
"--strip-debug-info",
"--O=release",
"--mlir-timing"
)
) )
} }

BIN
target/scala-2.13/-name-_2.13-0.1.0.jar Executable file → Normal file
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BIN
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2
target/streams/compile/_global/_global/compileOutputs/previous
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@ -1 +1 @@
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]] ["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$4.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$2.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$5.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$3.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]]

2
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@ -1,4 +1,4 @@
[debug] [root] Classpath dependencies List() [debug] [root] Classpath dependencies List()
[debug] [root] Dependencies from configurations List() [debug] [root] Dependencies from configurations List()
[debug] Bloop wrote the configuration of project 'root' to '/home/gh0s7/project/ddca/micore/.bloop/root.json' [debug] Bloop wrote the configuration of project 'root' to '/home/gh0s7/nfs/project/micore/.bloop/root.json'
[success] Generated .bloop/root.json [success] Generated .bloop/root.json

29
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2
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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar /home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar

2
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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes /home/gh0s7/nfs/project/micore/target/scala-2.13/classes

48
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@ -1,17 +1,59 @@
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak [debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/target/scala-2.13/classes.bak
[debug] About to delete class files: [debug] About to delete class files:
[debug]  Core$$anon$1.class
[debug]  Consts$.class
[debug]  Instructions$.class
[debug]  Core$$anon$4.class
[debug]  Core$$anon$2.class
[debug]  Top$.class
[debug]  Memory$$anon$1.class [debug]  Memory$$anon$1.class
[debug]  ImemPortIo.class [debug]  ImemPortIo.class
[debug]  Core.class
[debug]  Core$$anon$5.class
[debug]  Consts.class
[debug]  Core$$anon$3.class
[debug]  DmemPortIo.class [debug]  DmemPortIo.class
[debug]  Top$delayedInit$body.class
[debug]  Memory.class [debug]  Memory.class
[debug]  Top$$anon$1.class
[debug]  Instructions.class
[debug]  Top.class
[debug] We backup class files: [debug] We backup class files:
[debug]  Core$$anon$1.class
[debug]  Consts$.class
[debug]  Instructions$.class
[debug]  Core$$anon$4.class
[debug]  Core$$anon$2.class
[debug]  Top$.class
[debug]  Memory$$anon$1.class [debug]  Memory$$anon$1.class
[debug]  ImemPortIo.class [debug]  ImemPortIo.class
[debug]  Core.class
[debug]  Core$$anon$5.class
[debug]  Consts.class
[debug]  Core$$anon$3.class
[debug]  DmemPortIo.class [debug]  DmemPortIo.class
[debug]  Top$delayedInit$body.class
[debug]  Memory.class [debug]  Memory.class
[debug]  Top$$anon$1.class
[debug]  Instructions.class
[debug]  Top.class
[debug] Registering generated classes: [debug] Registering generated classes:
[debug]  DmemPortIo.class [debug]  Core$$anon$1.class
[debug]  Consts$.class
[debug]  Instructions$.class
[debug]  Core$$anon$4.class
[debug]  Core$$anon$2.class
[debug]  Top$.class
[debug]  Memory$$anon$1.class [debug]  Memory$$anon$1.class
[debug]  ImemPortIo.class [debug]  ImemPortIo.class
[debug]  Core.class
[debug]  Core$$anon$5.class
[debug]  Consts.class
[debug]  Core$$anon$3.class
[debug]  DmemPortIo.class
[debug]  Top$delayedInit$body.class
[debug]  Memory.class [debug]  Memory.class
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak [debug]  Top$$anon$1.class
[debug]  Instructions.class
[debug]  Top.class
[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/target/scala-2.13/classes.bak

2
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@ -1 +1 @@
-686303872 -1409454022

54
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@ -1,35 +1,43 @@
[debug] Packaging /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ... [debug] Packaging /home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ...
[debug] Input file mappings: [debug] Input file mappings:
[debug]  common [debug]  common
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common
[debug]  common/Consts$.class [debug]  common/Consts$.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts$.class
[debug]  common/Consts.class [debug]  common/Consts.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts.class
[debug]  common/Instructions$.class [debug]  common/Instructions$.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions$.class
[debug]  common/Instructions.class [debug]  common/Instructions.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions.class
[debug]  micore [debug]  micore
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore
[debug]  micore/Core$$anon$1.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class
[debug]  micore/Core.class [debug]  micore/Core.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core.class
[debug]  micore/DmemPortIo.class [debug]  micore/Core$$anon$1.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$1.class
[debug]  micore/Core$$anon$2.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$2.class
[debug]  micore/Core$$anon$3.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$3.class
[debug]  micore/Core$$anon$4.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$4.class
[debug]  micore/Core$$anon$5.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$5.class
[debug]  micore/ImemPortIo.class [debug]  micore/ImemPortIo.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/ImemPortIo.class
[debug]  micore/Memory$$anon$1.class [debug]  micore/DmemPortIo.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/DmemPortIo.class
[debug]  micore/Memory.class [debug]  micore/Memory.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory.class
[debug]  micore/Top$$anon$1.class [debug]  micore/Memory$$anon$1.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$$anon$1.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class
[debug]  micore/Top$.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$.class
[debug]  micore/Top$delayedInit$body.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class
[debug]  micore/Top.class [debug]  micore/Top.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top.class [debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top.class
[debug]  micore/Top$.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$.class
[debug]  micore/Top$$anon$1.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$$anon$1.class
[debug]  micore/Top$delayedInit$body.class
[debug]  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class
[debug] Done packaging. [debug] Done packaging.

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-1359482768 210211276

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@ -1 +1 @@
/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar /home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar

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/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar /home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar

2
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@ -1,4 +1,4 @@
[debug] [root-test] Classpath dependencies List() [debug] [root-test] Classpath dependencies List()
[debug] [root-test] Dependencies from configurations List(root) [debug] [root-test] Dependencies from configurations List(root)
[debug] Bloop wrote the configuration of project 'root-test' to '/home/gh0s7/project/ddca/micore/.bloop/root-test.json' [debug] Bloop wrote the configuration of project 'root-test' to '/home/gh0s7/nfs/project/micore/.bloop/root-test.json'
[success] Generated .bloop/root-test.json [success] Generated .bloop/root-test.json