Chisel code optimized
This commit is contained in:
1
.gitignore
vendored
1
.gitignore
vendored
@ -7,6 +7,7 @@
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.scalafmt.conf
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*.code-workspace
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target
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.vscode
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# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
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hs_err_pid*
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625
Top.sv
625
Top.sv
@ -16,12 +16,24 @@ module regfile_32x32(
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);
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reg [31:0] Memory[0:31];
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reg _R0_en_d0;
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reg [4:0] _R0_addr_d0;
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always @(posedge R0_clk) begin
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_R0_en_d0 <= R0_en;
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_R0_addr_d0 <= R0_addr;
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end // always @(posedge)
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reg _R1_en_d0;
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reg [4:0] _R1_addr_d0;
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always @(posedge R1_clk) begin
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_R1_en_d0 <= R1_en;
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_R1_addr_d0 <= R1_addr;
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end // always @(posedge)
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always @(posedge W0_clk) begin
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if (W0_en & 1'h1)
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Memory[W0_addr] <= W0_data;
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end // always @(posedge)
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assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
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assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
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assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
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assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
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endmodule
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module Core(
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@ -36,8 +48,6 @@ module Core(
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output io_exit
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);
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wire exe_jmp_flg;
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wire exe_br_flg;
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wire [31:0] _regfile_ext_R0_data;
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wire [31:0] _regfile_ext_R1_data;
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reg [31:0] id_reg_pc;
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@ -54,269 +64,249 @@ module Core(
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reg [31:0] exe_reg_imm_b_sext;
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reg [31:0] mem_reg_pc;
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reg [4:0] mem_reg_wb_addr;
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reg [31:0] mem_reg_alu_out;
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reg [31:0] mem_reg_rs2_data;
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reg [1:0] mem_reg_mem_wen;
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reg [1:0] mem_reg_rf_wen;
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reg [2:0] mem_reg_wb_sel;
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reg [31:0] mem_reg_alu_out;
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reg [1:0] mem_reg_mem_wen;
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reg [4:0] wb_reg_wb_addr;
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reg [1:0] wb_reg_rf_wen;
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reg [31:0] wb_reg_wb_data;
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reg [31:0] if_reg_pc;
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wire _id_inst_T = exe_br_flg | exe_jmp_flg;
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wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
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wire stall_flg =
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_id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
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& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
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& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
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wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
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wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
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assign exe_br_flg =
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exe_reg_exe_fun == 5'hB
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? exe_reg_op1_data == exe_reg_op2_data
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: exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
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assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
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wire [31:0] mem_wb_data =
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mem_reg_wb_sel == 3'h2
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? io_dmem_rdata
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: mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
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wire exe_br_flg =
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exe_reg_exe_fun == 5'hC
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? exe_reg_op1_data != exe_reg_op2_data
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: exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data;
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wire exe_jmp_flg = exe_reg_wb_sel == 3'h3;
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always @(posedge clock) begin
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if (reset) begin
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id_reg_pc <= 32'h0;
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automatic logic _id_inst_T = exe_br_flg | exe_jmp_flg;
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automatic logic _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
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automatic logic stall_flg;
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automatic logic [31:0] id_inst;
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automatic logic _id_rs2_data_T_2;
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automatic logic _id_rs2_data_T;
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automatic logic [31:0] _id_rs2_data_T_8;
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automatic logic [16:0] _GEN;
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automatic logic _csignals_T_5;
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automatic logic [19:0] _GEN_0;
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automatic logic _csignals_T_7;
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automatic logic _csignals_T_9;
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automatic logic _csignals_T_11;
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automatic logic _csignals_T_13;
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automatic logic _csignals_T_15;
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automatic logic _csignals_T_17;
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automatic logic _csignals_T_19;
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automatic logic [16:0] _GEN_1;
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automatic logic _csignals_T_21;
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automatic logic _csignals_T_23;
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automatic logic _csignals_T_25;
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automatic logic _csignals_T_27;
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automatic logic _csignals_T_29;
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automatic logic _csignals_T_31;
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automatic logic _csignals_T_33;
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automatic logic _csignals_T_35;
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automatic logic _csignals_T_37;
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automatic logic _GEN_2;
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automatic logic _GEN_3;
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automatic logic [1:0] csignals_1;
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automatic logic [2:0] _csignals_T_90;
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automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
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automatic logic [62:0] _exe_alu_out_T_8 =
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{31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
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automatic logic [31:0] exe_alu_out;
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stall_flg =
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_id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
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& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
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& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
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id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
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_id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
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_id_rs2_data_T = id_reg_inst[20:16] == 5'h0;
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_id_rs2_data_T_8 =
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id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
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? mem_reg_alu_out
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: id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
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? wb_reg_wb_data
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: _regfile_ext_R0_data;
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_GEN = {id_inst[31:26], id_inst[10:0]};
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_csignals_T_5 = _GEN == 17'h20;
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_GEN_0 = {id_inst[31:28], id_inst[15:0]};
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_csignals_T_7 = _GEN_0 == 20'h80000;
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_csignals_T_9 = _GEN == 17'h22;
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_csignals_T_11 = _GEN == 17'h24;
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_csignals_T_13 = _GEN == 17'h25;
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_csignals_T_15 = _GEN == 17'h26;
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_csignals_T_17 = _GEN_0 == 20'hC0000;
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_csignals_T_19 = _GEN_0 == 20'hD0000;
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_GEN_1 = {id_inst[30:20], id_inst[5:0]};
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_csignals_T_21 = _GEN_1 == 17'h0;
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_csignals_T_23 = _GEN_1 == 17'h2;
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_csignals_T_25 = _GEN_1 == 17'h3;
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_csignals_T_27 = _GEN == 17'h2A;
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_csignals_T_29 = _GEN_0 == 20'h40000;
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_csignals_T_31 = _GEN_0 == 20'h50000;
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_csignals_T_33 = id_inst == 32'hC000000;
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_csignals_T_35 = _GEN_0 == 20'h8;
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_csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
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_GEN_2 = _csignals_T_29 | _csignals_T_31;
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_GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
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csignals_1 =
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_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
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? 2'h0
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: _csignals_T_33 ? 2'h1 : _csignals_T_35 ? 2'h0 : {_csignals_T_37, 1'h0};
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_csignals_T_90 =
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_csignals_T_5
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? 3'h1
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: _csignals_T_7
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? 3'h2
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: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
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? 3'h1
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: _csignals_T_17 | _csignals_T_19
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? 3'h2
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: _GEN_3
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? 3'h1
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: _csignals_T_33
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? 3'h4
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: _csignals_T_35 ? 3'h0 : {_csignals_T_37, 2'h1};
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exe_alu_out =
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exe_reg_exe_fun == 5'hE
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? exe_reg_op1_data
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: exe_reg_exe_fun == 5'h9
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? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
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: exe_reg_exe_fun == 5'h8
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? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
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: exe_reg_exe_fun == 5'h7
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? exe_reg_op1_data >> _GEN_4
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: exe_reg_exe_fun == 5'h6
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? _exe_alu_out_T_8[31:0]
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: exe_reg_exe_fun == 5'h5
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? exe_reg_op1_data ^ exe_reg_op2_data
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: exe_reg_exe_fun == 5'h4
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? exe_reg_op1_data | exe_reg_op2_data
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: exe_reg_exe_fun == 5'h3
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? exe_reg_op1_data & exe_reg_op2_data
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: exe_reg_exe_fun == 5'h2
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? exe_reg_op1_data - exe_reg_op2_data
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: exe_reg_exe_fun == 5'h1
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? exe_reg_op1_data + exe_reg_op2_data
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: 32'h0;
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if (~stall_flg)
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id_reg_pc <= if_reg_pc;
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if (_id_inst_T)
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id_reg_inst <= 32'h0;
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exe_reg_pc <= 32'h0;
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exe_reg_wb_addr <= 5'h0;
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else if (~stall_flg)
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id_reg_inst <= io_imem_inst;
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exe_reg_pc <= id_reg_pc;
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exe_reg_wb_addr <= id_reg_inst[15:11];
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if (csignals_1 == 2'h0)
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exe_reg_op1_data <=
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id_reg_inst[25:21] == 5'h0
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? 32'h0
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: id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
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? mem_reg_alu_out
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: id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
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? wb_reg_wb_data
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: _regfile_ext_R1_data;
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else if (csignals_1 == 2'h1)
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exe_reg_op1_data <= id_reg_pc;
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else
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exe_reg_op1_data <= 32'h0;
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if (_csignals_T_90 == 3'h5)
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exe_reg_op2_data <= {id_inst[15:0], 16'h0};
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else if (_csignals_T_90 == 3'h4)
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exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
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else if (_csignals_T_90 == 3'h3 | _csignals_T_90 == 3'h2)
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exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
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else if (_csignals_T_90 != 3'h1 | _id_rs2_data_T)
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exe_reg_op2_data <= 32'h0;
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exe_reg_rs2_data <= 32'h0;
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exe_reg_exe_fun <= 5'h0;
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exe_reg_mem_wen <= 2'h0;
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else
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exe_reg_op2_data <= _id_rs2_data_T_8;
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exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8;
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if (_csignals_T_5 | _csignals_T_7)
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exe_reg_exe_fun <= 5'h1;
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else if (_csignals_T_9)
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exe_reg_exe_fun <= 5'h2;
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else if (_csignals_T_11)
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exe_reg_exe_fun <= 5'h3;
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else if (_csignals_T_13)
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exe_reg_exe_fun <= 5'h4;
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else if (_csignals_T_15)
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exe_reg_exe_fun <= 5'h5;
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else if (_csignals_T_17)
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exe_reg_exe_fun <= 5'h3;
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else if (_csignals_T_19)
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exe_reg_exe_fun <= 5'h4;
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else if (_csignals_T_21)
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exe_reg_exe_fun <= 5'h6;
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else if (_csignals_T_23)
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exe_reg_exe_fun <= 5'h7;
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else if (_csignals_T_25)
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exe_reg_exe_fun <= 5'h8;
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else if (_csignals_T_27)
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exe_reg_exe_fun <= 5'h9;
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else if (_csignals_T_29)
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exe_reg_exe_fun <= 5'hB;
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else if (_csignals_T_31)
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exe_reg_exe_fun <= 5'hC;
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else if (_csignals_T_33)
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exe_reg_exe_fun <= 5'h1;
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else if (_csignals_T_35)
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exe_reg_exe_fun <= 5'hE;
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else
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exe_reg_exe_fun <= {4'h0, _csignals_T_37};
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exe_reg_mem_wen <= 2'h0;
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if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
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| _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
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exe_reg_rf_wen <= 2'h1;
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exe_reg_wb_sel <= 3'h1;
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end
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else if (_GEN_2) begin
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exe_reg_rf_wen <= 2'h0;
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exe_reg_wb_sel <= 3'h0;
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end
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else if (_csignals_T_33) begin
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exe_reg_rf_wen <= 2'h1;
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exe_reg_wb_sel <= 3'h3;
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end
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else if (_csignals_T_35) begin
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exe_reg_rf_wen <= 2'h0;
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exe_reg_wb_sel <= 3'h0;
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exe_reg_imm_b_sext <= 32'h0;
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mem_reg_pc <= 32'h0;
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mem_reg_wb_addr <= 5'h0;
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mem_reg_rs2_data <= 32'h0;
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mem_reg_mem_wen <= 2'h0;
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mem_reg_rf_wen <= 2'h0;
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mem_reg_wb_sel <= 3'h0;
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mem_reg_alu_out <= 32'h0;
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wb_reg_wb_addr <= 5'h0;
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wb_reg_rf_wen <= 2'h0;
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wb_reg_wb_data <= 32'h0;
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if_reg_pc <= 32'h0;
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end
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else begin
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automatic logic _id_rs2_data_T_2;
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automatic logic [31:0] id_rs2_data;
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automatic logic [16:0] _GEN = {id_inst[31:26], id_inst[10:0]};
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automatic logic _csignals_T_5 = _GEN == 17'h20;
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automatic logic [19:0] _GEN_0 = {id_inst[31:28], id_inst[15:0]};
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automatic logic _csignals_T_7 = _GEN_0 == 20'h80000;
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automatic logic _csignals_T_9;
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automatic logic _csignals_T_11;
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automatic logic _csignals_T_13;
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automatic logic _csignals_T_15;
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automatic logic _csignals_T_17;
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automatic logic _csignals_T_19;
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automatic logic [16:0] _GEN_1 = {id_inst[30:20], id_inst[5:0]};
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automatic logic _csignals_T_21;
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automatic logic _csignals_T_23;
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automatic logic _csignals_T_25;
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automatic logic _csignals_T_27;
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automatic logic _csignals_T_29;
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automatic logic _csignals_T_31;
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automatic logic _csignals_T_33;
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automatic logic _csignals_T_35;
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automatic logic _csignals_T_37;
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automatic logic _GEN_2;
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automatic logic _GEN_3;
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automatic logic [1:0] csignals_1;
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automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
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automatic logic [62:0] _exe_alu_out_T_14 =
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{31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
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automatic logic [31:0] exe_alu_out;
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automatic logic [7:0][31:0] _GEN_5;
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_id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
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id_rs2_data =
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id_inst[20:16] == 5'h0
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? 32'h0
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: id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
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? mem_wb_data
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: id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
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? wb_reg_wb_data
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: _regfile_ext_R0_data;
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_csignals_T_9 = _GEN == 17'h22;
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_csignals_T_11 = _GEN == 17'h24;
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_csignals_T_13 = _GEN == 17'h25;
|
||||
_csignals_T_15 = _GEN == 17'h26;
|
||||
_csignals_T_17 = _GEN_0 == 20'hC0000;
|
||||
_csignals_T_19 = _GEN_0 == 20'hD0000;
|
||||
_csignals_T_21 = _GEN_1 == 17'h0;
|
||||
_csignals_T_23 = _GEN_1 == 17'h2;
|
||||
_csignals_T_25 = _GEN_1 == 17'h3;
|
||||
_csignals_T_27 = _GEN == 17'h2A;
|
||||
_csignals_T_29 = _GEN_0 == 20'h40000;
|
||||
_csignals_T_31 = _GEN_0 == 20'h50000;
|
||||
_csignals_T_33 = id_inst == 32'hC000000;
|
||||
_csignals_T_35 = _GEN_0 == 20'h8;
|
||||
_csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
|
||||
_GEN_2 = _csignals_T_29 | _csignals_T_31;
|
||||
_GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
|
||||
csignals_1 =
|
||||
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
|
||||
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
|
||||
? 2'h0
|
||||
: _csignals_T_33 ? 2'h1 : _csignals_T_35 ? 2'h0 : {_csignals_T_37, 1'h0};
|
||||
exe_alu_out =
|
||||
exe_reg_exe_fun == 5'h1
|
||||
? exe_reg_op1_data + exe_reg_op2_data
|
||||
: exe_reg_exe_fun == 5'h2
|
||||
? exe_reg_op1_data - exe_reg_op2_data
|
||||
: exe_reg_exe_fun == 5'h3
|
||||
? exe_reg_op1_data & exe_reg_op2_data
|
||||
: exe_reg_exe_fun == 5'h4
|
||||
? exe_reg_op1_data | exe_reg_op2_data
|
||||
: exe_reg_exe_fun == 5'h5
|
||||
? exe_reg_op1_data ^ exe_reg_op2_data
|
||||
: exe_reg_exe_fun == 5'h6
|
||||
? _exe_alu_out_T_14[31:0]
|
||||
: exe_reg_exe_fun == 5'h7
|
||||
? exe_reg_op1_data >> _GEN_4
|
||||
: exe_reg_exe_fun == 5'h8
|
||||
? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
|
||||
: exe_reg_exe_fun == 5'h9
|
||||
? {31'h0,
|
||||
$signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
|
||||
: exe_reg_exe_fun == 5'hE
|
||||
? exe_reg_op1_data
|
||||
: 32'h0;
|
||||
if (~stall_flg)
|
||||
id_reg_pc <= if_reg_pc;
|
||||
if (_id_inst_T)
|
||||
id_reg_inst <= 32'h0;
|
||||
else if (~stall_flg)
|
||||
id_reg_inst <= io_imem_inst;
|
||||
exe_reg_pc <= id_reg_pc;
|
||||
exe_reg_wb_addr <= id_inst[15:11];
|
||||
if (csignals_1 == 2'h0) begin
|
||||
if (id_inst[25:21] == 5'h0)
|
||||
exe_reg_op1_data <= 32'h0;
|
||||
else if (id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2)
|
||||
exe_reg_op1_data <= mem_wb_data;
|
||||
else if (id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5)
|
||||
exe_reg_op1_data <= wb_reg_wb_data;
|
||||
else
|
||||
exe_reg_op1_data <= _regfile_ext_R1_data;
|
||||
end
|
||||
else if (csignals_1 == 2'h1)
|
||||
exe_reg_op1_data <= id_reg_pc;
|
||||
else
|
||||
exe_reg_op1_data <= 32'h0;
|
||||
_GEN_5 =
|
||||
{{32'h0},
|
||||
{32'h0},
|
||||
{{id_inst[15:0], 16'h0}},
|
||||
{{{4{id_inst[25]}}, id_inst[25:0], 2'h0}},
|
||||
{{{16{id_inst[15]}}, id_inst[15:0]}},
|
||||
{{{16{id_inst[15]}}, id_inst[15:0]}},
|
||||
{id_rs2_data},
|
||||
{32'h0}};
|
||||
exe_reg_op2_data <=
|
||||
_GEN_5[_csignals_T_5
|
||||
? 3'h1
|
||||
: _csignals_T_7
|
||||
? 3'h2
|
||||
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
|
||||
? 3'h1
|
||||
: _csignals_T_17 | _csignals_T_19
|
||||
? 3'h2
|
||||
: _GEN_3
|
||||
? 3'h1
|
||||
: _csignals_T_33
|
||||
? 3'h4
|
||||
: _csignals_T_35 ? 3'h0 : {_csignals_T_37, 2'h1}];
|
||||
exe_reg_rs2_data <= id_rs2_data;
|
||||
if (_csignals_T_5 | _csignals_T_7)
|
||||
exe_reg_exe_fun <= 5'h1;
|
||||
else if (_csignals_T_9)
|
||||
exe_reg_exe_fun <= 5'h2;
|
||||
else if (_csignals_T_11)
|
||||
exe_reg_exe_fun <= 5'h3;
|
||||
else if (_csignals_T_13)
|
||||
exe_reg_exe_fun <= 5'h4;
|
||||
else if (_csignals_T_15)
|
||||
exe_reg_exe_fun <= 5'h5;
|
||||
else if (_csignals_T_17)
|
||||
exe_reg_exe_fun <= 5'h3;
|
||||
else if (_csignals_T_19)
|
||||
exe_reg_exe_fun <= 5'h4;
|
||||
else if (_csignals_T_21)
|
||||
exe_reg_exe_fun <= 5'h6;
|
||||
else if (_csignals_T_23)
|
||||
exe_reg_exe_fun <= 5'h7;
|
||||
else if (_csignals_T_25)
|
||||
exe_reg_exe_fun <= 5'h8;
|
||||
else if (_csignals_T_27)
|
||||
exe_reg_exe_fun <= 5'h9;
|
||||
else if (_csignals_T_29)
|
||||
exe_reg_exe_fun <= 5'hB;
|
||||
else if (_csignals_T_31)
|
||||
exe_reg_exe_fun <= 5'hC;
|
||||
else if (_csignals_T_33)
|
||||
exe_reg_exe_fun <= 5'h1;
|
||||
else if (_csignals_T_35)
|
||||
exe_reg_exe_fun <= 5'hE;
|
||||
else
|
||||
exe_reg_exe_fun <= {4'h0, _csignals_T_37};
|
||||
exe_reg_mem_wen <= 2'h0;
|
||||
if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
|
||||
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
|
||||
| _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
|
||||
exe_reg_rf_wen <= 2'h1;
|
||||
exe_reg_wb_sel <= 3'h1;
|
||||
end
|
||||
else if (_GEN_2) begin
|
||||
exe_reg_rf_wen <= 2'h0;
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
end
|
||||
else if (_csignals_T_33) begin
|
||||
exe_reg_rf_wen <= 2'h1;
|
||||
exe_reg_wb_sel <= 3'h3;
|
||||
end
|
||||
else if (_csignals_T_35) begin
|
||||
exe_reg_rf_wen <= 2'h0;
|
||||
exe_reg_wb_sel <= 3'h0;
|
||||
end
|
||||
else begin
|
||||
exe_reg_rf_wen <= {1'h0, _csignals_T_37};
|
||||
exe_reg_wb_sel <= {2'h0, _csignals_T_37};
|
||||
end
|
||||
exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
|
||||
mem_reg_pc <= exe_reg_pc;
|
||||
mem_reg_wb_addr <= exe_reg_wb_addr;
|
||||
mem_reg_rs2_data <= exe_reg_rs2_data;
|
||||
mem_reg_mem_wen <= exe_reg_mem_wen;
|
||||
mem_reg_rf_wen <= exe_reg_rf_wen;
|
||||
mem_reg_wb_sel <= exe_reg_wb_sel;
|
||||
mem_reg_alu_out <= exe_alu_out;
|
||||
wb_reg_wb_addr <= mem_reg_wb_addr;
|
||||
wb_reg_rf_wen <= mem_reg_rf_wen;
|
||||
wb_reg_wb_data <= mem_wb_data;
|
||||
if (exe_br_flg)
|
||||
if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
|
||||
else if (exe_jmp_flg)
|
||||
if_reg_pc <= exe_alu_out;
|
||||
else if (~stall_flg)
|
||||
if_reg_pc <= if_reg_pc + 32'h4;
|
||||
exe_reg_rf_wen <= {1'h0, _csignals_T_37};
|
||||
exe_reg_wb_sel <= {2'h0, _csignals_T_37};
|
||||
end
|
||||
exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
|
||||
mem_reg_pc <= exe_reg_pc;
|
||||
mem_reg_wb_addr <= exe_reg_wb_addr;
|
||||
mem_reg_alu_out <= exe_alu_out;
|
||||
mem_reg_rs2_data <= exe_reg_rs2_data;
|
||||
mem_reg_rf_wen <= exe_reg_rf_wen;
|
||||
mem_reg_wb_sel <= exe_reg_wb_sel;
|
||||
mem_reg_mem_wen <= exe_reg_mem_wen;
|
||||
wb_reg_wb_addr <= mem_reg_wb_addr;
|
||||
wb_reg_rf_wen <= mem_reg_rf_wen;
|
||||
wb_reg_wb_data <=
|
||||
mem_reg_wb_sel == 3'h3
|
||||
? mem_reg_pc + 32'h4
|
||||
: mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out;
|
||||
if (reset)
|
||||
if_reg_pc <= 32'h0;
|
||||
else if (exe_br_flg)
|
||||
if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
|
||||
else if (exe_jmp_flg)
|
||||
if_reg_pc <= exe_alu_out;
|
||||
else if (~stall_flg)
|
||||
if_reg_pc <= if_reg_pc + 32'h4;
|
||||
end // always @(posedge)
|
||||
regfile_32x32 regfile_ext (
|
||||
.R0_addr (id_inst[20:16]),
|
||||
.R0_addr (id_reg_inst[20:16]),
|
||||
.R0_en (1'h1),
|
||||
.R0_clk (clock),
|
||||
.R0_data (_regfile_ext_R0_data),
|
||||
.R1_addr (id_inst[25:21]),
|
||||
.R1_addr (id_reg_inst[25:21]),
|
||||
.R1_en (1'h1),
|
||||
.R1_clk (clock),
|
||||
.R1_data (_regfile_ext_R1_data),
|
||||
@ -333,80 +323,44 @@ module Core(
|
||||
endmodule
|
||||
|
||||
// VCS coverage exclude_file
|
||||
module mem_8192x8(
|
||||
input [12:0] R0_addr,
|
||||
module mem_512x32(
|
||||
input [8:0] R0_addr,
|
||||
input R0_en,
|
||||
R0_clk,
|
||||
output [7:0] R0_data,
|
||||
input [12:0] R1_addr,
|
||||
output [31:0] R0_data,
|
||||
input [8:0] R1_addr,
|
||||
input R1_en,
|
||||
R1_clk,
|
||||
output [7:0] R1_data,
|
||||
input [12:0] R2_addr,
|
||||
input R2_en,
|
||||
R2_clk,
|
||||
output [7:0] R2_data,
|
||||
input [12:0] R3_addr,
|
||||
input R3_en,
|
||||
R3_clk,
|
||||
output [7:0] R3_data,
|
||||
input [12:0] R4_addr,
|
||||
input R4_en,
|
||||
R4_clk,
|
||||
output [7:0] R4_data,
|
||||
input [12:0] R5_addr,
|
||||
input R5_en,
|
||||
R5_clk,
|
||||
output [7:0] R5_data,
|
||||
input [12:0] R6_addr,
|
||||
input R6_en,
|
||||
R6_clk,
|
||||
output [7:0] R6_data,
|
||||
input [12:0] R7_addr,
|
||||
input R7_en,
|
||||
R7_clk,
|
||||
output [7:0] R7_data,
|
||||
input [12:0] W0_addr,
|
||||
output [31:0] R1_data,
|
||||
input [8:0] W0_addr,
|
||||
input W0_en,
|
||||
W0_clk,
|
||||
input [7:0] W0_data,
|
||||
input [12:0] W1_addr,
|
||||
input W1_en,
|
||||
W1_clk,
|
||||
input [7:0] W1_data,
|
||||
input [12:0] W2_addr,
|
||||
input W2_en,
|
||||
W2_clk,
|
||||
input [7:0] W2_data,
|
||||
input [12:0] W3_addr,
|
||||
input W3_en,
|
||||
W3_clk,
|
||||
input [7:0] W3_data
|
||||
input [31:0] W0_data
|
||||
);
|
||||
|
||||
reg [7:0] Memory[0:8191];
|
||||
reg [31:0] Memory[0:511];
|
||||
reg _R0_en_d0;
|
||||
reg [8:0] _R0_addr_d0;
|
||||
always @(posedge R0_clk) begin
|
||||
_R0_en_d0 <= R0_en;
|
||||
_R0_addr_d0 <= R0_addr;
|
||||
end // always @(posedge)
|
||||
reg _R1_en_d0;
|
||||
reg [8:0] _R1_addr_d0;
|
||||
always @(posedge R1_clk) begin
|
||||
_R1_en_d0 <= R1_en;
|
||||
_R1_addr_d0 <= R1_addr;
|
||||
end // always @(posedge)
|
||||
always @(posedge W0_clk) begin
|
||||
if (W0_en & 1'h1)
|
||||
Memory[W0_addr] <= W0_data;
|
||||
if (W1_en & 1'h1)
|
||||
Memory[W1_addr] <= W1_data;
|
||||
if (W2_en & 1'h1)
|
||||
Memory[W2_addr] <= W2_data;
|
||||
if (W3_en & 1'h1)
|
||||
Memory[W3_addr] <= W3_data;
|
||||
end // always @(posedge)
|
||||
`ifdef ENABLE_INITIAL_MEM_
|
||||
initial
|
||||
$readmemh("src/hex/mem.hex", Memory);
|
||||
`endif // ENABLE_INITIAL_MEM_
|
||||
assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
|
||||
assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
|
||||
assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
|
||||
assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
|
||||
assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
|
||||
assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
|
||||
assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
|
||||
assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
|
||||
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
|
||||
assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
|
||||
endmodule
|
||||
|
||||
module Memory(
|
||||
@ -419,71 +373,20 @@ module Memory(
|
||||
input [31:0] io_dmem_wdata
|
||||
);
|
||||
|
||||
wire [7:0] _mem_ext_R0_data;
|
||||
wire [7:0] _mem_ext_R1_data;
|
||||
wire [7:0] _mem_ext_R2_data;
|
||||
wire [7:0] _mem_ext_R3_data;
|
||||
wire [7:0] _mem_ext_R4_data;
|
||||
wire [7:0] _mem_ext_R5_data;
|
||||
wire [7:0] _mem_ext_R6_data;
|
||||
wire [7:0] _mem_ext_R7_data;
|
||||
wire [12:0] _io_dmem_rdata_T_1 = io_dmem_addr[12:0] + 13'h1;
|
||||
wire [12:0] _io_dmem_rdata_T_4 = io_dmem_addr[12:0] + 13'h2;
|
||||
wire [12:0] _io_dmem_rdata_T_7 = io_dmem_addr[12:0] + 13'h3;
|
||||
mem_8192x8 mem_ext (
|
||||
.R0_addr (io_imem_addr[12:0] + 13'h3),
|
||||
mem_512x32 mem_ext (
|
||||
.R0_addr (io_imem_addr[10:2]),
|
||||
.R0_en (1'h1),
|
||||
.R0_clk (clock),
|
||||
.R0_data (_mem_ext_R0_data),
|
||||
.R1_addr (io_imem_addr[12:0] + 13'h2),
|
||||
.R0_data (io_imem_inst),
|
||||
.R1_addr (io_dmem_addr[10:2]),
|
||||
.R1_en (1'h1),
|
||||
.R1_clk (clock),
|
||||
.R1_data (_mem_ext_R1_data),
|
||||
.R2_addr (io_imem_addr[12:0] + 13'h1),
|
||||
.R2_en (1'h1),
|
||||
.R2_clk (clock),
|
||||
.R2_data (_mem_ext_R2_data),
|
||||
.R3_addr (io_imem_addr[12:0]),
|
||||
.R3_en (1'h1),
|
||||
.R3_clk (clock),
|
||||
.R3_data (_mem_ext_R3_data),
|
||||
.R4_addr (_io_dmem_rdata_T_7),
|
||||
.R4_en (1'h1),
|
||||
.R4_clk (clock),
|
||||
.R4_data (_mem_ext_R4_data),
|
||||
.R5_addr (_io_dmem_rdata_T_4),
|
||||
.R5_en (1'h1),
|
||||
.R5_clk (clock),
|
||||
.R5_data (_mem_ext_R5_data),
|
||||
.R6_addr (_io_dmem_rdata_T_1),
|
||||
.R6_en (1'h1),
|
||||
.R6_clk (clock),
|
||||
.R6_data (_mem_ext_R6_data),
|
||||
.R7_addr (io_dmem_addr[12:0]),
|
||||
.R7_en (1'h1),
|
||||
.R7_clk (clock),
|
||||
.R7_data (_mem_ext_R7_data),
|
||||
.W0_addr (_io_dmem_rdata_T_7),
|
||||
.R1_data (io_dmem_rdata),
|
||||
.W0_addr (io_dmem_addr[10:2]),
|
||||
.W0_en (io_dmem_wen),
|
||||
.W0_clk (clock),
|
||||
.W0_data (io_dmem_wdata[7:0]),
|
||||
.W1_addr (_io_dmem_rdata_T_4),
|
||||
.W1_en (io_dmem_wen),
|
||||
.W1_clk (clock),
|
||||
.W1_data (io_dmem_wdata[15:8]),
|
||||
.W2_addr (_io_dmem_rdata_T_1),
|
||||
.W2_en (io_dmem_wen),
|
||||
.W2_clk (clock),
|
||||
.W2_data (io_dmem_wdata[23:16]),
|
||||
.W3_addr (io_dmem_addr[12:0]),
|
||||
.W3_en (io_dmem_wen),
|
||||
.W3_clk (clock),
|
||||
.W3_data (io_dmem_wdata[31:24])
|
||||
.W0_data (io_dmem_wdata)
|
||||
);
|
||||
assign io_imem_inst =
|
||||
{_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
|
||||
assign io_dmem_rdata =
|
||||
{_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
|
||||
endmodule
|
||||
|
||||
module Top(
|
||||
|
||||
@ -1 +1 @@
|
||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
|
||||
{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
|
||||
@ -1,3 +1,8 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = true, force = false[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/project/"), "micore-build-build-build")...[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/project/"), "micore-build-build-build")[0m
|
||||
[0m[[0m[33mwarn[0m] [0m[0msbt-bloop_2.12_1.0-2.0.6.jar no longer exists at /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mnot up to date. inChanged = false, force = false[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mUpdating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/project/"), "micore-build-build-build")...[0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mUpdating [0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mResolved dependencies[0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mFetching artifacts of [0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mFetched artifacts of [0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/project/"), "micore-build-build-build")[0m
|
||||
|
||||
@ -1 +1 @@
|
||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
|
||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
|
||||
@ -1 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
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|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
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||||
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak[0m
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||||
|
||||
File diff suppressed because one or more lines are too long
@ -1 +1 @@
|
||||
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|
||||
/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1 +1 @@
|
||||
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|
||||
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|
||||
|
||||
@ -1 +1 @@
|
||||
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||||
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|
||||
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|
||||
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||||
[0m[[0m[0mdebug[0m] [0m[0mDone updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")[0m
|
||||
[0m[[0m[33mwarn[0m] [0m[0msbt-bloop_2.12_1.0-2.0.6-sources.jar no longer exists at /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6-sources.jar[0m
|
||||
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|
||||
|
||||
@ -1 +1 @@
|
||||
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|
||||
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|
||||
@ -1,4 +1,4 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[micore-build-build] Classpath dependencies List()[0m
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[0m[[0m[0mdebug[0m] [0m[0m[micore-build-build] Dependencies from configurations List()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mBloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json'[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mBloop wrote the configuration of project 'micore-build-build' to '/home/gh0s7/nfs/project/micore/project/project/.bloop/micore-build-build.json'[0m
|
||||
[0m[[0m[32msuccess[0m] [0m[0mGenerated .bloop/micore-build-build.json[0m
|
||||
|
||||
@ -1 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
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|
||||
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|
||||
[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
@ -1 +1 @@
|
||||
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|
||||
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|
||||
|
||||
@ -1 +1 @@
|
||||
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|
||||
/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
||||
@ -1 +1 @@
|
||||
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|
||||
/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
|
||||
@ -1 +1 @@
|
||||
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|
||||
/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
||||
@ -1 +1 @@
|
||||
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|
||||
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|
||||
@ -1 +1 @@
|
||||
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|
||||
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|
||||
@ -1,4 +1,4 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[micore-build] Classpath dependencies List()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[micore-build] Dependencies from configurations List()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mBloop wrote the configuration of project 'micore-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/.bloop/micore-build.json'[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mBloop wrote the configuration of project 'micore-build' to '/home/gh0s7/nfs/project/micore/project/.bloop/micore-build.json'[0m
|
||||
[0m[[0m[32msuccess[0m] [0m[0mGenerated .bloop/micore-build.json[0m
|
||||
|
||||
@ -1 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes
|
||||
/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mAbout to delete class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mWe backup class files:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mCreated transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mRemoving the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak[0m
|
||||
|
||||
@ -1 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
|
||||
@ -1 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes
|
||||
/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
||||
@ -1 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
|
||||
|
||||
@ -1 +1 @@
|
||||
/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes
|
||||
/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes
|
||||
|
||||
@ -4,7 +4,6 @@ import chisel3._
|
||||
import chisel3.util._
|
||||
import common.Consts._
|
||||
import common.Instructions._
|
||||
import os.list
|
||||
|
||||
class Core extends Module {
|
||||
val io = IO(new Bundle {
|
||||
@ -13,253 +12,245 @@ class Core extends Module {
|
||||
val exit = Output(Bool())
|
||||
})
|
||||
|
||||
val regfile = Mem(32, UInt(WORD_LEN.W))
|
||||
// Block RAM for data memory
|
||||
val regfile = SyncReadMem(32, UInt(WORD_LEN.W))
|
||||
|
||||
// ********* Pipeline Registers *********
|
||||
// IF/ID state
|
||||
val id_reg_pc = RegInit(0.U(WORD_LEN.W))
|
||||
val id_reg_inst = RegInit(0.U(WORD_LEN.W))
|
||||
val id_reg = Reg(new Bundle {
|
||||
val pc = UInt(WORD_LEN.W)
|
||||
val inst = UInt(WORD_LEN.W)
|
||||
})
|
||||
|
||||
// ID/EX state
|
||||
val exe_reg_pc = RegInit(0.U(WORD_LEN.W))
|
||||
val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
|
||||
val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W))
|
||||
val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W))
|
||||
val exe_reg_rs2_data = RegInit(0.U(WORD_LEN.W))
|
||||
val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W))
|
||||
val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
|
||||
val exe_reg_rf_wen = RegInit(0.U(REN_LEN.W))
|
||||
val exe_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
|
||||
val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W))
|
||||
val exe_reg_imm_s_sext = RegInit(0.U(WORD_LEN.W))
|
||||
val exe_reg_imm_b_sext = RegInit(0.U(WORD_LEN.W))
|
||||
val exe_reg_imm_u_shifted = RegInit(0.U(WORD_LEN.W))
|
||||
val exe_reg = Reg(new Bundle {
|
||||
val pc = UInt(WORD_LEN.W)
|
||||
val wb_addr = UInt(ADDR_LEN.W)
|
||||
val op1_data = UInt(WORD_LEN.W)
|
||||
val op2_data = UInt(WORD_LEN.W)
|
||||
val rs2_data = UInt(WORD_LEN.W)
|
||||
val exe_fun = UInt(EXE_FUN_LEN.W)
|
||||
val mem_wen = UInt(MEN_LEN.W)
|
||||
val rf_wen = UInt(REN_LEN.W)
|
||||
val wb_sel = UInt(WB_SEL_LEN.W)
|
||||
val imm_b_sext = UInt(WORD_LEN.W)
|
||||
})
|
||||
|
||||
// EX/MEM state
|
||||
val mem_reg_pc = RegInit(0.U(WORD_LEN.W))
|
||||
val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
|
||||
val mem_reg_op1_data = RegInit(0.U(WORD_LEN.W))
|
||||
val mem_reg_rs2_data = RegInit(0.U(WORD_LEN.W))
|
||||
val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
|
||||
val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W))
|
||||
val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
|
||||
val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W))
|
||||
val mem_reg = Reg(new Bundle {
|
||||
val pc = UInt(WORD_LEN.W)
|
||||
val wb_addr = UInt(ADDR_LEN.W)
|
||||
val alu_out = UInt(WORD_LEN.W)
|
||||
val rs2_data = UInt(WORD_LEN.W)
|
||||
val rf_wen = UInt(REN_LEN.W)
|
||||
val wb_sel = UInt(WB_SEL_LEN.W)
|
||||
val mem_wen = UInt(MEN_LEN.W)
|
||||
})
|
||||
|
||||
// MEM/WB state
|
||||
val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
|
||||
val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W))
|
||||
val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W))
|
||||
val wb_reg = Reg(new Bundle {
|
||||
val wb_addr = UInt(ADDR_LEN.W)
|
||||
val rf_wen = UInt(REN_LEN.W)
|
||||
val wb_data = UInt(WORD_LEN.W)
|
||||
})
|
||||
|
||||
// ********* Instruction Fetch (IF) Stage *********
|
||||
val if_reg_pc = RegInit(START_ADDR)
|
||||
io.imem.addr := if_reg_pc
|
||||
val if_inst = io.imem.inst
|
||||
|
||||
val stall_flg = Wire(Bool()) // 停顿标志
|
||||
val exe_br_flg = Wire(Bool()) // 跳转标志
|
||||
val exe_br_target = Wire(UInt(WORD_LEN.W)) // 跳转目标地址
|
||||
val exe_jmp_flg = Wire(Bool()) // 跳转标志
|
||||
val exe_alu_out = Wire(UInt(WORD_LEN.W)) // ALU输出
|
||||
val stall_flg = Wire(Bool())
|
||||
val exe_br_flg = Wire(Bool())
|
||||
val exe_br_target = Wire(UInt(WORD_LEN.W))
|
||||
val exe_jmp_flg = Wire(Bool())
|
||||
val exe_alu_out = Wire(UInt(WORD_LEN.W))
|
||||
|
||||
val if_pc_plus4 = if_reg_pc + 4.U(WORD_LEN.W)
|
||||
val if_pc_next =
|
||||
MuxCase(
|
||||
if_pc_plus4,
|
||||
Seq(
|
||||
exe_br_flg -> exe_br_target,
|
||||
exe_jmp_flg -> exe_alu_out,
|
||||
stall_flg -> if_reg_pc
|
||||
)
|
||||
val if_pc_next = MuxCase(
|
||||
if_pc_plus4,
|
||||
Seq(
|
||||
exe_br_flg -> exe_br_target,
|
||||
exe_jmp_flg -> exe_alu_out,
|
||||
stall_flg -> if_reg_pc
|
||||
)
|
||||
)
|
||||
if_reg_pc := if_pc_next
|
||||
|
||||
// ********* IF/ID Stage *********
|
||||
id_reg_pc := Mux(stall_flg, id_reg_pc, if_reg_pc)
|
||||
id_reg_inst := MuxCase(
|
||||
id_reg.pc := Mux(stall_flg, id_reg.pc, if_reg_pc)
|
||||
id_reg.inst := MuxCase(
|
||||
if_inst,
|
||||
Seq(
|
||||
(exe_br_flg || exe_jmp_flg) -> BUBBLE,
|
||||
stall_flg -> id_reg_inst
|
||||
stall_flg -> id_reg.inst
|
||||
)
|
||||
)
|
||||
|
||||
// ********* Decode (ID) Stage *********
|
||||
val id_rs1_addr_b = id_reg_inst(25, 21)
|
||||
val id_rs2_addr_b = id_reg_inst(20, 16)
|
||||
val id_rs1_addr = id_reg.inst(25, 21)
|
||||
val id_rs2_addr = id_reg.inst(20, 16)
|
||||
val id_wb_addr = id_reg.inst(15, 11)
|
||||
|
||||
// 与EX数据冒险
|
||||
// Data Hazard
|
||||
val id_rs1_data_hazard =
|
||||
(exe_reg_rf_wen === REN_S) && (id_rs1_addr_b =/= 0.U) && (id_rs1_addr_b === exe_reg_wb_addr)
|
||||
(exe_reg.rf_wen === REN_S) && (id_rs1_addr =/= 0.U) && (id_rs1_addr === exe_reg.wb_addr)
|
||||
val id_rs2_data_hazard =
|
||||
(exe_reg_rf_wen === REN_S) && (id_rs2_addr_b =/= 0.U) && (id_rs2_addr_b === exe_reg_wb_addr)
|
||||
(exe_reg.rf_wen === REN_S) && (id_rs2_addr =/= 0.U) && (id_rs2_addr === exe_reg.wb_addr)
|
||||
stall_flg := (id_rs1_data_hazard || id_rs2_data_hazard)
|
||||
|
||||
val id_inst =
|
||||
Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst)
|
||||
val id_inst = Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg.inst)
|
||||
|
||||
val id_rs1_addr = id_inst(25, 21)
|
||||
val id_rs2_addr = id_inst(20, 16)
|
||||
val id_wb_addr = id_inst(15, 11)
|
||||
val mem_wb_data = Wire(UInt(WORD_LEN.W))
|
||||
val id_rs1_data = MuxCase(
|
||||
regfile(id_rs1_addr),
|
||||
Seq(
|
||||
(id_rs1_addr === 0.U) -> 0.U(WORD_LEN.W),
|
||||
((id_rs1_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通
|
||||
((id_rs1_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通
|
||||
)
|
||||
)
|
||||
val id_rs2_data = MuxCase(
|
||||
regfile(id_rs2_addr),
|
||||
Seq(
|
||||
(id_rs2_addr === 0.U) -> 0.U(WORD_LEN.W),
|
||||
((id_rs2_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通
|
||||
((id_rs2_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通
|
||||
)
|
||||
)
|
||||
|
||||
val id_imm_i = id_inst(15, 0)
|
||||
val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i)
|
||||
val id_imm_s = id_inst(15, 0)
|
||||
val id_imm_s_sext = Cat(Fill(16, id_imm_s(15)), id_imm_s)
|
||||
val id_imm_b = id_inst(15, 0)
|
||||
val id_imm_b_sext = Cat(Fill(16, id_imm_b(15)), id_imm_b)
|
||||
val id_imm_j = id_inst(25, 0)
|
||||
val id_imm_j_sext = Cat(Fill(4, id_imm_j(25)), id_imm_j, 0.U(2.W))
|
||||
val id_imm_u = id_inst(15, 0)
|
||||
val id_imm_u_shifted = Cat(id_imm_u, Fill(16, 0.U(1.W)))
|
||||
|
||||
val csignals =
|
||||
ListLookup(
|
||||
id_inst,
|
||||
List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
|
||||
Array(
|
||||
LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_MEM),
|
||||
SW -> List(ALU_ADD, OP1_RS1, OP2_IMS, MEN_S, REN_X, WB_X),
|
||||
ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
|
||||
SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
|
||||
ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
|
||||
SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
|
||||
BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
|
||||
JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC),
|
||||
JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X),
|
||||
LUI -> List(ALU_ADD, OP1_X, OP2_IMU, MEN_X, REN_S, WB_ALU)
|
||||
val id_rs1_data = Mux(
|
||||
id_rs1_addr === 0.U,
|
||||
0.U(WORD_LEN.W),
|
||||
Mux(
|
||||
(id_rs1_addr === mem_reg.wb_addr) && (mem_reg.rf_wen === REN_S),
|
||||
mem_reg.alu_out,
|
||||
Mux(
|
||||
(id_rs1_addr === wb_reg.wb_addr) && (wb_reg.rf_wen === REN_S),
|
||||
wb_reg.wb_data,
|
||||
regfile(id_rs1_addr)
|
||||
)
|
||||
)
|
||||
|
||||
val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil =
|
||||
csignals
|
||||
|
||||
val id_op1_data = MuxCase(
|
||||
)
|
||||
val id_rs2_data = Mux(
|
||||
id_rs2_addr === 0.U,
|
||||
0.U(WORD_LEN.W),
|
||||
Seq(
|
||||
(id_op1_sel === OP1_RS1) -> id_rs1_data,
|
||||
(id_op1_sel === OP1_PC) -> id_reg_pc
|
||||
Mux(
|
||||
(id_rs2_addr === mem_reg.wb_addr) && (mem_reg.rf_wen === REN_S),
|
||||
mem_reg.alu_out,
|
||||
Mux(
|
||||
(id_rs2_addr === wb_reg.wb_addr) && (wb_reg.rf_wen === REN_S),
|
||||
wb_reg.wb_data,
|
||||
regfile(id_rs2_addr)
|
||||
)
|
||||
)
|
||||
)
|
||||
val id_op2_data = MuxCase(
|
||||
0.U(WORD_LEN.W),
|
||||
|
||||
// 立即数扩展
|
||||
val id_imm_i_sext = Cat(Fill(16, id_inst(15)), id_inst(15, 0))
|
||||
val id_imm_b_sext = Cat(Fill(16, id_inst(15)), id_inst(15, 0))
|
||||
|
||||
// 控制信号解码
|
||||
val csignals = ListLookup(
|
||||
id_inst,
|
||||
List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
|
||||
Array(
|
||||
LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_MEM),
|
||||
SW -> List(ALU_ADD, OP1_RS1, OP2_IMS, MEN_S, REN_X, WB_X),
|
||||
ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
|
||||
SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
|
||||
ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
|
||||
SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
|
||||
BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
|
||||
BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
|
||||
JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC),
|
||||
JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X),
|
||||
LUI -> List(ALU_ADD, OP1_X, OP2_IMU, MEN_X, REN_S, WB_ALU)
|
||||
)
|
||||
)
|
||||
|
||||
val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil = csignals
|
||||
|
||||
val id_op1_data = Mux(
|
||||
id_op1_sel === OP1_RS1,
|
||||
id_rs1_data,
|
||||
Mux(id_op1_sel === OP1_PC, id_reg.pc, 0.U(WORD_LEN.W))
|
||||
)
|
||||
val id_op2_data = MuxLookup(
|
||||
id_op2_sel,
|
||||
0.U(WORD_LEN.W)
|
||||
)(
|
||||
Seq(
|
||||
(id_op2_sel === OP2_RS2) -> id_rs2_data,
|
||||
(id_op2_sel === OP2_IMI) -> id_imm_i_sext,
|
||||
(id_op2_sel === OP2_IMS) -> id_imm_s_sext,
|
||||
(id_op2_sel === OP2_IMJ) -> id_imm_j_sext,
|
||||
(id_op2_sel === OP2_IMU) -> id_imm_u_shifted
|
||||
OP2_RS2 -> id_rs2_data,
|
||||
OP2_IMI -> id_imm_i_sext,
|
||||
OP2_IMS -> id_imm_i_sext,
|
||||
OP2_IMJ -> Cat(Fill(4, id_inst(25)), id_inst(25, 0), 0.U(2.W)),
|
||||
OP2_IMU -> Cat(id_inst(15, 0), Fill(16, 0.U))
|
||||
)
|
||||
)
|
||||
|
||||
// ********* Decode/Execute (ID/EX) Stage *********
|
||||
exe_reg_pc := id_reg_pc
|
||||
exe_reg_op1_data := id_op1_data
|
||||
exe_reg_op2_data := id_op2_data
|
||||
exe_reg_rs2_data := id_rs2_data
|
||||
exe_reg_wb_addr := id_wb_addr
|
||||
exe_reg_wb_sel := id_wb_sel
|
||||
exe_reg_mem_wen := id_mem_wen
|
||||
exe_reg_rf_wen := id_rf_wen
|
||||
exe_reg_imm_b_sext := id_imm_b_sext
|
||||
exe_reg_imm_i_sext := id_imm_i_sext
|
||||
exe_reg_imm_s_sext := id_imm_s_sext
|
||||
exe_reg_imm_u_shifted := id_imm_u_shifted
|
||||
exe_reg_exe_fun := id_exe_fun
|
||||
exe_reg.pc := id_reg.pc
|
||||
exe_reg.op1_data := id_op1_data
|
||||
exe_reg.op2_data := id_op2_data
|
||||
exe_reg.rs2_data := id_rs2_data
|
||||
exe_reg.wb_addr := id_wb_addr
|
||||
exe_reg.wb_sel := id_wb_sel
|
||||
exe_reg.mem_wen := id_mem_wen
|
||||
exe_reg.rf_wen := id_rf_wen
|
||||
exe_reg.imm_b_sext := id_imm_b_sext
|
||||
exe_reg.exe_fun := id_exe_fun
|
||||
|
||||
// ********* Execute (EX) Stage *********
|
||||
exe_alu_out := MuxCase(
|
||||
0.U(WORD_LEN.W),
|
||||
exe_alu_out := MuxLookup(
|
||||
exe_reg.exe_fun,
|
||||
0.U(WORD_LEN.W)
|
||||
)(
|
||||
Seq(
|
||||
(exe_reg_exe_fun === ALU_ADD) -> (exe_reg_op1_data + exe_reg_op2_data),
|
||||
(exe_reg_exe_fun === ALU_SUB) -> (exe_reg_op1_data - exe_reg_op2_data),
|
||||
(exe_reg_exe_fun === ALU_AND) -> (exe_reg_op1_data & exe_reg_op2_data),
|
||||
(exe_reg_exe_fun === ALU_OR) -> (exe_reg_op1_data | exe_reg_op2_data),
|
||||
(exe_reg_exe_fun === ALU_XOR) -> (exe_reg_op1_data ^ exe_reg_op2_data),
|
||||
(exe_reg_exe_fun === ALU_SLL) -> (exe_reg_op1_data << exe_reg_op2_data(
|
||||
4,
|
||||
0
|
||||
))(31, 0),
|
||||
(exe_reg_exe_fun === ALU_SRL) -> (exe_reg_op1_data >> exe_reg_op2_data(
|
||||
4,
|
||||
0
|
||||
)).asUInt,
|
||||
(exe_reg_exe_fun === ALU_SRA) -> (exe_reg_op1_data.asSInt >> exe_reg_op2_data(
|
||||
4,
|
||||
0
|
||||
)).asUInt,
|
||||
(exe_reg_exe_fun === ALU_SLT) -> (exe_reg_op1_data.asSInt < exe_reg_op2_data.asSInt).asUInt,
|
||||
(exe_reg_exe_fun === ALU_COPY1) -> exe_reg_op1_data
|
||||
ALU_ADD -> (exe_reg.op1_data + exe_reg.op2_data),
|
||||
ALU_SUB -> (exe_reg.op1_data - exe_reg.op2_data),
|
||||
ALU_AND -> (exe_reg.op1_data & exe_reg.op2_data),
|
||||
ALU_OR -> (exe_reg.op1_data | exe_reg.op2_data),
|
||||
ALU_XOR -> (exe_reg.op1_data ^ exe_reg.op2_data),
|
||||
ALU_SLL -> (exe_reg.op1_data << exe_reg.op2_data(4, 0))(31, 0),
|
||||
ALU_SRL -> (exe_reg.op1_data >> exe_reg.op2_data(4, 0)).asUInt,
|
||||
ALU_SRA -> (exe_reg.op1_data.asSInt >> exe_reg.op2_data(4, 0)).asUInt,
|
||||
ALU_SLT -> (exe_reg.op1_data.asSInt < exe_reg.op2_data.asSInt).asUInt,
|
||||
ALU_COPY1 -> exe_reg.op1_data
|
||||
)
|
||||
)
|
||||
|
||||
exe_br_flg := MuxCase(
|
||||
false.B,
|
||||
exe_br_flg := MuxLookup(
|
||||
exe_reg.exe_fun,
|
||||
false.B
|
||||
)(
|
||||
Seq(
|
||||
(exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data),
|
||||
(exe_reg_exe_fun === BR_BNE) -> (exe_reg_op1_data =/= exe_reg_op2_data)
|
||||
BR_BEQ -> (exe_reg.op1_data === exe_reg.op2_data),
|
||||
BR_BNE -> (exe_reg.op1_data =/= exe_reg.op2_data)
|
||||
)
|
||||
)
|
||||
|
||||
exe_br_target := exe_reg_pc + exe_reg_imm_b_sext
|
||||
exe_br_target := exe_reg.pc + exe_reg.imm_b_sext
|
||||
exe_jmp_flg := (exe_reg.wb_sel === WB_PC)
|
||||
|
||||
exe_jmp_flg := (exe_reg_wb_sel === WB_PC)
|
||||
// ********* Execute/Memory (EX/MEM) Stage *********
|
||||
mem_reg.pc := exe_reg.pc
|
||||
mem_reg.wb_addr := exe_reg.wb_addr
|
||||
mem_reg.alu_out := exe_alu_out
|
||||
mem_reg.rs2_data := exe_reg.rs2_data
|
||||
mem_reg.rf_wen := exe_reg.rf_wen
|
||||
mem_reg.wb_sel := exe_reg.wb_sel
|
||||
mem_reg.mem_wen := exe_reg.mem_wen
|
||||
|
||||
// ********** Execute/Memory (EX/MEM) Stage ***********
|
||||
mem_reg_pc := exe_reg_pc
|
||||
mem_reg_op1_data := exe_reg_op1_data
|
||||
mem_reg_rs2_data := exe_reg_rs2_data
|
||||
mem_reg_wb_addr := exe_reg_wb_addr
|
||||
mem_reg_alu_out := exe_alu_out
|
||||
mem_reg_rf_wen := exe_reg_rf_wen
|
||||
mem_reg_wb_sel := exe_reg_wb_sel
|
||||
mem_reg_mem_wen := exe_reg_mem_wen
|
||||
// ********* Memory (MEM) Stage *********
|
||||
io.dmem.addr := mem_reg.alu_out
|
||||
io.dmem.wen := mem_reg.mem_wen
|
||||
io.dmem.wdata := mem_reg.rs2_data
|
||||
|
||||
// ********* Memory (MEM) Stage ***********
|
||||
io.dmem.addr := mem_reg_alu_out
|
||||
io.dmem.wen := mem_reg_mem_wen
|
||||
io.dmem.wdata := mem_reg_rs2_data
|
||||
|
||||
mem_wb_data := MuxCase(
|
||||
mem_reg_alu_out,
|
||||
val mem_wb_data = MuxLookup(
|
||||
mem_reg.wb_sel,
|
||||
mem_reg.alu_out
|
||||
)(
|
||||
Seq(
|
||||
(mem_reg_wb_sel === WB_MEM) -> io.dmem.rdata,
|
||||
(mem_reg_wb_sel === WB_PC) -> (mem_reg_pc + 4.U(WORD_LEN.W))
|
||||
WB_MEM -> io.dmem.rdata,
|
||||
WB_PC -> (mem_reg.pc + 4.U(WORD_LEN.W))
|
||||
)
|
||||
)
|
||||
// ********** Memory/Write Back (MEM/WB) Stage ***********
|
||||
wb_reg_wb_data := mem_wb_data
|
||||
wb_reg_rf_wen := mem_reg_rf_wen
|
||||
wb_reg_wb_addr := mem_reg_wb_addr
|
||||
|
||||
// ********* Memory/Write Back (MEM/WB) Stage *********
|
||||
wb_reg.wb_addr := mem_reg.wb_addr
|
||||
wb_reg.rf_wen := mem_reg.rf_wen
|
||||
wb_reg.wb_data := mem_wb_data
|
||||
|
||||
// ********* Write Back (WB) Stage *********
|
||||
when(wb_reg_rf_wen === REN_S) { regfile(wb_reg_wb_addr) := wb_reg_wb_data }
|
||||
|
||||
io.exit := (id_reg_inst === UNIMP)
|
||||
when(wb_reg.rf_wen === REN_S) {
|
||||
regfile(wb_reg.wb_addr) := wb_reg.wb_data
|
||||
}
|
||||
|
||||
io.exit := (id_reg.inst === UNIMP)
|
||||
}
|
||||
|
||||
@ -23,28 +23,16 @@ class Memory extends Module {
|
||||
val dmem = new DmemPortIo
|
||||
})
|
||||
|
||||
val mem = Mem(8192, UInt(8.W))
|
||||
// val mem = Mem(8192, UInt(8.W))
|
||||
val mem = SyncReadMem(512, UInt(WORD_LEN.W))
|
||||
|
||||
loadMemoryFromFileInline(mem, "src/hex/mem.hex")
|
||||
|
||||
io.imem.inst := Cat(
|
||||
mem(io.imem.addr),
|
||||
mem(io.imem.addr + 1.U(WORD_LEN.W)),
|
||||
mem(io.imem.addr + 2.U(WORD_LEN.W)),
|
||||
mem(io.imem.addr + 3.U(WORD_LEN.W))
|
||||
)
|
||||
io.imem.inst := mem.read(io.imem.addr >> 2)
|
||||
|
||||
io.dmem.rdata := Cat(
|
||||
mem(io.dmem.addr),
|
||||
mem(io.dmem.addr + 1.U(WORD_LEN.W)),
|
||||
mem(io.dmem.addr + 2.U(WORD_LEN.W)),
|
||||
mem(io.dmem.addr + 3.U(WORD_LEN.W))
|
||||
)
|
||||
io.dmem.rdata := mem.read(io.dmem.addr >> 2)
|
||||
|
||||
when(io.dmem.wen) {
|
||||
mem(io.dmem.addr) := io.dmem.wdata(31, 24)
|
||||
mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(23, 16)
|
||||
mem(io.dmem.addr + 2.U(WORD_LEN.W)) := io.dmem.wdata(15, 8)
|
||||
mem(io.dmem.addr + 3.U(WORD_LEN.W)) := io.dmem.wdata(7, 0)
|
||||
mem.write(io.dmem.addr >> 2, io.dmem.wdata)
|
||||
}
|
||||
}
|
||||
|
||||
@ -23,6 +23,11 @@ class Top extends Module {
|
||||
object Top extends App {
|
||||
ChiselStage.emitSystemVerilogFile(
|
||||
new Top,
|
||||
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
|
||||
firtoolOpts = Array(
|
||||
"--disable-all-randomization",
|
||||
"--strip-debug-info",
|
||||
"--O=release",
|
||||
"--mlir-timing"
|
||||
)
|
||||
)
|
||||
}
|
||||
|
||||
BIN
target/scala-2.13/-name-_2.13-0.1.0.jar
Executable file → Normal file
BIN
target/scala-2.13/-name-_2.13-0.1.0.jar
Executable file → Normal file
Binary file not shown.
BIN
target/scala-2.13/zinc/inc_compile_2.13.zip
Executable file → Normal file
BIN
target/scala-2.13/zinc/inc_compile_2.13.zip
Executable file → Normal file
Binary file not shown.
@ -1 +1 @@
|
||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]]
|
||||
["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$4.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$2.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$5.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$3.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]]
|
||||
@ -1,4 +1,4 @@
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[root] Classpath dependencies List()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[root] Dependencies from configurations List()[0m
|
||||
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|
||||
[0m[[0m[0mdebug[0m] [0m[0mDone packaging.[0m
|
||||
|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
[0m[[0m[0mdebug[0m] [0m[0mBloop wrote the configuration of project 'root-test' to '/home/gh0s7/project/ddca/micore/.bloop/root-test.json'[0m
|
||||
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|
||||
[0m[[0m[32msuccess[0m] [0m[0mGenerated .bloop/root-test.json[0m
|
||||
|
||||
Reference in New Issue
Block a user