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Add single cycle edition

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CGH0S7
2024-12-31 01:30:15 +08:00
parent de44f7d8d3
commit b4cb98d8a9
126 changed files with 1242 additions and 629 deletions
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test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir
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@ -81,13 +81,13 @@ circuit TopOrigin :
node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 65:31]
node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 65:31]
node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21]
node id_rs1_addr_b = bits(id_reg_inst, 19, 15) @[src/main/scala/micore/Core.scala 87:34]
node id_rs1_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 87:34]
node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:50]
node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32]
node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:77]
node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:59]
node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 94:21]
node id_rs2_addr_b = bits(id_reg_inst, 24, 20) @[src/main/scala/micore/Core.scala 88:34]
node id_rs2_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 88:34]
node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 94:50]
node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 94:32]
node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 94:77]
@ -127,25 +127,17 @@ circuit TopOrigin :
node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 221:65]
node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("ha")) @[src/main/scala/micore/Core.scala 222:24]
node _exe_alu_out_T_29 = lt(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 222:59]
node _exe_alu_out_T_30 = eq(exe_reg_exe_fun, UInt<5>("hd")) @[src/main/scala/micore/Core.scala 223:24]
node _exe_alu_out_T_31 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 223:60]
node _exe_alu_out_T_32 = tail(_exe_alu_out_T_31, 1) @[src/main/scala/micore/Core.scala 223:60]
node _exe_alu_out_T_33 = not(UInt<32>("h1")) @[src/main/scala/micore/Core.scala 223:83]
node _exe_alu_out_T_34 = and(_exe_alu_out_T_32, _exe_alu_out_T_33) @[src/main/scala/micore/Core.scala 223:80]
node _exe_alu_out_T_35 = eq(exe_reg_exe_fun, UInt<5>("he")) @[src/main/scala/micore/Core.scala 225:24]
node _exe_alu_out_T_36 = mux(_exe_alu_out_T_35, exe_reg_op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_37 = mux(_exe_alu_out_T_30, _exe_alu_out_T_34, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_38 = mux(_exe_alu_out_T_28, _exe_alu_out_T_29, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_39 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_38) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_40 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_39) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_41 = mux(_exe_alu_out_T_16, _exe_alu_out_T_18, _exe_alu_out_T_40) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_42 = mux(_exe_alu_out_T_12, _exe_alu_out_T_15, _exe_alu_out_T_41) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_43 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_42) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_44 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_43) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_45 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_44) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_46 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_45) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_47 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_46) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node exe_alu_out = _exe_alu_out_T_47 @[src/main/scala/micore/Core.scala 201:15 63:25]
node _exe_alu_out_T_30 = mux(_exe_alu_out_T_28, _exe_alu_out_T_29, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_31 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_32 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_31) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_33 = mux(_exe_alu_out_T_16, _exe_alu_out_T_18, _exe_alu_out_T_32) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_34 = mux(_exe_alu_out_T_12, _exe_alu_out_T_15, _exe_alu_out_T_33) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_35 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_34) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_36 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_37 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_38 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_alu_out_T_39 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_38) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node exe_alu_out = _exe_alu_out_T_39 @[src/main/scala/micore/Core.scala 201:15 63:25]
node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 232:24]
node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 232:57]
@ -162,10 +154,10 @@ circuit TopOrigin :
node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 77:19]
node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 81:19]
node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h0"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20000000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 98:21]
node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 98:36]
node id_inst = mux(_id_inst_T_1, UInt<32>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 98:8]
node id_inst = mux(_id_inst_T_1, UInt<32>("h20000000"), id_reg_inst) @[src/main/scala/micore/Core.scala 98:8]
node id_rs1_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 100:28]
node id_rs2_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 101:28]
node id_wb_addr = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 102:27]
@ -218,23 +210,23 @@ circuit TopOrigin :
node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_2 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_4 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_4 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_6 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_8 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_8 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_10 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_10 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_11 = eq(UInt<6>("h24"), _csignals_T_10) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_12 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_12 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_14 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_14 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_16 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_18 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_20 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_20 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_21 = eq(UInt<6>("h2a"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_22 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_23 = eq(UInt<31>("h40000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
@ -246,134 +238,126 @@ circuit TopOrigin :
node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_30 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_32 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_32 = and(id_inst, UInt<34>("h3f000003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_33 = eq(UInt<4>("h8"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_34 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_35 = eq(UInt<30>("h30000000"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_36 = and(id_inst, UInt<34>("h3ff800000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_37 = eq(UInt<32>("hf0000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_38 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_39 = eq(UInt<1>("h0"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_40 = mux(_csignals_T_39, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_41 = mux(_csignals_T_37, UInt<5>("h0"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_42 = mux(_csignals_T_35, UInt<5>("h0"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_43 = mux(_csignals_T_33, UInt<5>("h0"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_44 = mux(_csignals_T_31, UInt<5>("h8"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_45 = mux(_csignals_T_29, UInt<5>("h7"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_46 = mux(_csignals_T_27, UInt<5>("h6"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_47 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_48 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_49 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_50 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_51 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_52 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_53 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_54 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_55 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_56 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_57 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_58 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_59 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_60 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_61 = mux(_csignals_T_35, UInt<2>("h2"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_62 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_63 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_64 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_65 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_66 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_67 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_68 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_69 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_70 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_71 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_72 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_73 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_74 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_75 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_76 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_77 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_78 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_79 = mux(_csignals_T_37, UInt<3>("h5"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_80 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_81 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_82 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_83 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_84 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_85 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_86 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_87 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_88 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_89 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_90 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_91 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_92 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_93 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_94 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_95 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_96 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_97 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_98 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_99 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_100 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_101 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_102 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_103 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_104 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_105 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_106 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_107 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_108 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_109 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_110 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_111 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_112 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_113 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_114 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_115 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_3 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_116 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_117 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_118 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_119 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_120 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_121 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_122 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_123 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_124 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_125 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_126 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_127 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_128 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_129 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_130 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_131 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_132 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_133 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_134 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_135 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_136 = mux(_csignals_T_37, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_137 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_138 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_139 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_138) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_140 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_139) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_141 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_140) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_142 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_141) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_143 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_142) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_144 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_145 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_146 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_147 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_146) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_148 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_147) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_149 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_148) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_150 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_149) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_151 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_150) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_152 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_151) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_153 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_152) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_153) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_36 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_37 = eq(UInt<30>("h20000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_38 = mux(_csignals_T_37, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_39 = mux(_csignals_T_35, UInt<5>("h0"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_40 = mux(_csignals_T_33, UInt<5>("h0"), _csignals_T_39) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_41 = mux(_csignals_T_31, UInt<5>("h8"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_42 = mux(_csignals_T_29, UInt<5>("h7"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_43 = mux(_csignals_T_27, UInt<5>("h6"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_44 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_45 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_46 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_47 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_48 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_49 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_50 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_51 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_52 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_53 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_54 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_55 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_56 = mux(_csignals_T_37, UInt<2>("h0"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_57 = mux(_csignals_T_35, UInt<2>("h2"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_58 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_59 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_60 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_61 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_62 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_63 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_64 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_65 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_66 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_67 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_68 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_69 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_70 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_71 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_72 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_73 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_74 = mux(_csignals_T_37, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_75 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_76 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_77 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_78 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_79 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_80 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_81 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_82 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_83 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_84 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_85 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_86 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_87 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_88 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_89 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_90 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_91 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_92 = mux(_csignals_T_37, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_93 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_94 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_95 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_96 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_97 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_98 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_99 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_100 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_101 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_102 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_103 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_104 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_105 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_106 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_107 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_108 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_109 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_3 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_110 = mux(_csignals_T_37, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_111 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_112 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_113 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_114 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_115 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_116 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_117 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_118 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_119 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_120 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_121 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_122 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_123 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_124 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_125 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_126 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_127 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_128 = mux(_csignals_T_37, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_129 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_130 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_131 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_132 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_133 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_134 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_135 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_136 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_137 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_138 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_139 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_138) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_140 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_139) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_141 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_140) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_142 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_141) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_143 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_142) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_144 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_145 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 171:19]
node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 172:19]
node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
@ -423,6 +407,12 @@ circuit TopOrigin :
node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9]
node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9]
node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9]
node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9]
node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9]
node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 291:9]
node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 291:9]
node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 292:9]
node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 292:9]
io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 56:16]
io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 253:16]
io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 254:15]
@ -467,7 +457,7 @@ circuit TopOrigin :
wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 268:18 50:{31,31}]
wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 267:17 51:{30,30}]
wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 266:18 52:{31,31}]
if_reg_pc <= mux(reset, UInt<32>("h400000"), if_pc_next) @[src/main/scala/micore/Core.scala 55:{26,26} 74:13]
if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 55:{26,26} 74:13]
printf(clock, and(and(UInt<1>("h1"), _T_2), UInt<1>("h1")), "---------------------\n") : printf @[src/main/scala/micore/Core.scala 275:9]
printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 276:9]
printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 277:9]
@ -475,14 +465,17 @@ circuit TopOrigin :
printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_4 @[src/main/scala/micore/Core.scala 279:9]
printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_rs1_data: 0x%x\n", id_rs1_data) : printf_5 @[src/main/scala/micore/Core.scala 280:9]
printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_rs2_data: 0x%x\n", id_rs2_data) : printf_6 @[src/main/scala/micore/Core.scala 281:9]
printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_7 @[src/main/scala/micore/Core.scala 282:9]
printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", id_op1_data) : printf_8 @[src/main/scala/micore/Core.scala 283:9]
printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", id_op2_data) : printf_9 @[src/main/scala/micore/Core.scala 284:9]
printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_10 @[src/main/scala/micore/Core.scala 285:9]
printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_11 @[src/main/scala/micore/Core.scala 286:9]
printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_12 @[src/main/scala/micore/Core.scala 287:9]
printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_13 @[src/main/scala/micore/Core.scala 288:9]
printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "---------------------\n") : printf_14 @[src/main/scala/micore/Core.scala 289:9]
printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_exe_fun: 0x%x\n", csignals_0) : printf_7 @[src/main/scala/micore/Core.scala 282:9]
printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_op1_sel: 0x%x\n", csignals_1) : printf_8 @[src/main/scala/micore/Core.scala 283:9]
printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_op2_sel: 0x%x\n", csignals_2) : printf_9 @[src/main/scala/micore/Core.scala 284:9]
printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_10 @[src/main/scala/micore/Core.scala 285:9]
printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", id_op1_data) : printf_11 @[src/main/scala/micore/Core.scala 286:9]
printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", id_op2_data) : printf_12 @[src/main/scala/micore/Core.scala 287:9]
printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_13 @[src/main/scala/micore/Core.scala 288:9]
printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_14 @[src/main/scala/micore/Core.scala 289:9]
printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_15 @[src/main/scala/micore/Core.scala 290:9]
printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_16 @[src/main/scala/micore/Core.scala 291:9]
printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "---------------------\n") : printf_17 @[src/main/scala/micore/Core.scala 292:9]
module Memory : @[src/main/scala/micore/Memory.scala 24:7]
input clock : Clock @[src/main/scala/micore/Memory.scala 24:7]

452
test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir Executable file
View File

@ -0,0 +1,452 @@
FIRRTL version 1.2.0
circuit TopOrigin :
module Core : @[src/main/scala/sicore/Core.scala 8:7]
input clock : Clock @[src/main/scala/sicore/Core.scala 8:7]
input reset : UInt<1> @[src/main/scala/sicore/Core.scala 8:7]
output io_imem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 9:14]
input io_imem_inst : UInt<32> @[src/main/scala/sicore/Core.scala 9:14]
output io_dmem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 9:14]
input io_dmem_rdata : UInt<32> @[src/main/scala/sicore/Core.scala 9:14]
output io_dmem_wen : UInt<1> @[src/main/scala/sicore/Core.scala 9:14]
output io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Core.scala 9:14]
output io_exit : UInt<1> @[src/main/scala/sicore/Core.scala 9:14]
mem regfile : @[src/main/scala/sicore/Core.scala 16:20]
data-type => UInt<32>
depth => 32
read-latency => 0
write-latency => 1
reader => rs_data_MPORT
reader => rt_data_MPORT
writer => MPORT
read-under-write => undefined
reg pc_reg : UInt<32>, clock with :
reset => (UInt<1>("h0"), pc_reg) @[src/main/scala/sicore/Core.scala 19:23]
node _pc_plus4_T = add(pc_reg, UInt<32>("h4")) @[src/main/scala/sicore/Core.scala 22:25]
node pc_plus4 = tail(_pc_plus4_T, 1) @[src/main/scala/sicore/Core.scala 22:25]
node _jmp_flg_T = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/sicore/Core.scala 25:23]
node _jmp_flg_T_1 = eq(UInt<30>("h30000000"), _jmp_flg_T) @[src/main/scala/sicore/Core.scala 25:23]
node _jmp_flg_T_2 = and(io_imem_inst, UInt<34>("h3f000003f")) @[src/main/scala/sicore/Core.scala 25:39]
node _jmp_flg_T_3 = eq(UInt<4>("h8"), _jmp_flg_T_2) @[src/main/scala/sicore/Core.scala 25:39]
node jmp_flg = or(_jmp_flg_T_1, _jmp_flg_T_3) @[src/main/scala/sicore/Core.scala 25:31]
node _csignals_T = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_2 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_4 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_6 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_8 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_10 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_11 = eq(UInt<6>("h24"), _csignals_T_10) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_12 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_14 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_16 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_18 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_20 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_21 = eq(UInt<6>("h2a"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_22 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_23 = eq(UInt<31>("h40000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_24 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_25 = eq(UInt<31>("h50000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_26 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_27 = eq(UInt<1>("h0"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_28 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_30 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_32 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_33 = eq(UInt<30>("h30000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_34 = and(io_imem_inst, UInt<34>("h3f000003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_35 = eq(UInt<4>("h8"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
node _csignals_T_36 = mux(_csignals_T_35, UInt<5>("hd"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_37 = mux(_csignals_T_33, UInt<5>("h1"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_38 = mux(_csignals_T_31, UInt<5>("h8"), _csignals_T_37) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_39 = mux(_csignals_T_29, UInt<5>("h7"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_40 = mux(_csignals_T_27, UInt<5>("h6"), _csignals_T_39) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_41 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_42 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_43 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_44 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_45 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_46 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_47 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_48 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_49 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_50 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_51 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_52 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _alu_out_T = eq(csignals_0, UInt<5>("h1")) @[src/main/scala/sicore/Core.scala 97:16]
node _csignals_T_53 = mux(_csignals_T_35, UInt<2>("h1"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_54 = mux(_csignals_T_33, UInt<2>("h2"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_55 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_56 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_57 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_58 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_59 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_60 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_61 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_62 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_63 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_64 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_65 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_66 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_67 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_68 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_69 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 79:16]
node rs_addr = bits(io_imem_inst, 25, 21) @[src/main/scala/sicore/Core.scala 39:21]
node _rs_data_T = neq(rs_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 42:30]
node rs_data = mux(_rs_data_T, regfile.rs_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 42:20]
node _op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/sicore/Core.scala 80:16]
node _op1_data_T_2 = mux(_op1_data_T_1, pc_reg, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node op1_data = mux(_op1_data_T, rs_data, _op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _csignals_T_70 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_71 = mux(_csignals_T_33, UInt<3>("h4"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_72 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_73 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_74 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_75 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_76 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_77 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_78 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_79 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_80 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_81 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_82 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_83 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_84 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_85 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_86 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 87:16]
node rt_addr = bits(io_imem_inst, 20, 16) @[src/main/scala/sicore/Core.scala 40:21]
node _rt_data_T = neq(rt_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 43:30]
node rt_data = mux(_rt_data_T, regfile.rt_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 43:20]
node _op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 88:16]
node imm_i = bits(io_imem_inst, 15, 0) @[src/main/scala/sicore/Core.scala 44:19]
node _imm_i_sext_T = bits(imm_i, 15, 15) @[src/main/scala/sicore/Core.scala 45:38]
node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/sicore/Core.scala 45:28]
node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) @[src/main/scala/sicore/Core.scala 45:23]
node _op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/sicore/Core.scala 89:16]
node _imm_j_T = bits(io_imem_inst, 25, 0) @[src/main/scala/sicore/Core.scala 46:23]
node _imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/sicore/Core.scala 46:36]
node imm_j = cat(_imm_j_T, _imm_j_T_1) @[src/main/scala/sicore/Core.scala 46:18]
node _op2_data_T_3 = mux(_op2_data_T_2, imm_j, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _op2_data_T_4 = mux(_op2_data_T_1, imm_i_sext, _op2_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node op2_data = mux(_op2_data_T, rt_data, _op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _alu_out_T_1 = add(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 97:42]
node _alu_out_T_2 = tail(_alu_out_T_1, 1) @[src/main/scala/sicore/Core.scala 97:42]
node _alu_out_T_3 = eq(csignals_0, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 98:16]
node _alu_out_T_4 = sub(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 98:42]
node _alu_out_T_5 = tail(_alu_out_T_4, 1) @[src/main/scala/sicore/Core.scala 98:42]
node _alu_out_T_6 = eq(csignals_0, UInt<5>("h3")) @[src/main/scala/sicore/Core.scala 99:16]
node _alu_out_T_7 = and(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 99:42]
node _alu_out_T_8 = eq(csignals_0, UInt<5>("h4")) @[src/main/scala/sicore/Core.scala 100:16]
node _alu_out_T_9 = or(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 100:41]
node _alu_out_T_10 = eq(csignals_0, UInt<5>("h5")) @[src/main/scala/sicore/Core.scala 101:16]
node _alu_out_T_11 = xor(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 101:42]
node _alu_out_T_12 = eq(csignals_0, UInt<5>("h6")) @[src/main/scala/sicore/Core.scala 102:16]
node _alu_out_T_13 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 102:53]
node _alu_out_T_14 = dshl(op1_data, _alu_out_T_13) @[src/main/scala/sicore/Core.scala 102:42]
node _alu_out_T_15 = bits(_alu_out_T_14, 31, 0) @[src/main/scala/sicore/Core.scala 102:60]
node _alu_out_T_16 = eq(csignals_0, UInt<5>("h7")) @[src/main/scala/sicore/Core.scala 103:16]
node _alu_out_T_17 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 103:53]
node _alu_out_T_18 = dshr(op1_data, _alu_out_T_17) @[src/main/scala/sicore/Core.scala 103:42]
node _alu_out_T_19 = eq(csignals_0, UInt<5>("h8")) @[src/main/scala/sicore/Core.scala 104:16]
node _alu_out_T_20 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 104:42]
node _alu_out_T_21 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 104:60]
node _alu_out_T_22 = dshr(_alu_out_T_20, _alu_out_T_21) @[src/main/scala/sicore/Core.scala 104:49]
node _alu_out_T_23 = asUInt(_alu_out_T_22) @[src/main/scala/sicore/Core.scala 104:68]
node _alu_out_T_24 = eq(csignals_0, UInt<5>("h9")) @[src/main/scala/sicore/Core.scala 105:16]
node _alu_out_T_25 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 105:42]
node _alu_out_T_26 = asSInt(op2_data) @[src/main/scala/sicore/Core.scala 105:60]
node _alu_out_T_27 = lt(_alu_out_T_25, _alu_out_T_26) @[src/main/scala/sicore/Core.scala 105:49]
node _alu_out_T_28 = eq(csignals_0, UInt<5>("hd")) @[src/main/scala/sicore/Core.scala 106:16]
node _alu_out_T_29 = mux(_alu_out_T_28, op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _alu_out_T_30 = mux(_alu_out_T_24, _alu_out_T_27, _alu_out_T_29) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _alu_out_T_31 = mux(_alu_out_T_19, _alu_out_T_23, _alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _alu_out_T_32 = mux(_alu_out_T_16, _alu_out_T_18, _alu_out_T_31) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _alu_out_T_33 = mux(_alu_out_T_12, _alu_out_T_15, _alu_out_T_32) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _alu_out_T_34 = mux(_alu_out_T_10, _alu_out_T_11, _alu_out_T_33) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _alu_out_T_35 = mux(_alu_out_T_8, _alu_out_T_9, _alu_out_T_34) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _alu_out_T_36 = mux(_alu_out_T_6, _alu_out_T_7, _alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _alu_out_T_37 = mux(_alu_out_T_3, _alu_out_T_5, _alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _alu_out_T_38 = mux(_alu_out_T, _alu_out_T_2, _alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node alu_out = _alu_out_T_38 @[src/main/scala/sicore/Core.scala 26:21 94:11]
node _pc_next_T = mux(jmp_flg, alu_out, pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _br_flg_T = eq(csignals_0, UInt<5>("hb")) @[src/main/scala/sicore/Core.scala 113:16]
node _br_flg_T_1 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 113:41]
node _br_flg_T_2 = eq(csignals_0, UInt<5>("hc")) @[src/main/scala/sicore/Core.scala 114:16]
node _br_flg_T_3 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 114:42]
node _br_flg_T_4 = eq(_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 114:31]
node _br_flg_T_5 = mux(_br_flg_T_2, _br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _br_flg_T_6 = mux(_br_flg_T, _br_flg_T_1, _br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node br_flg = _br_flg_T_6 @[src/main/scala/sicore/Core.scala 110:10 23:20]
node _br_target_T = dshl(imm_i_sext, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 119:37]
node _br_target_T_1 = add(pc_reg, _br_target_T) @[src/main/scala/sicore/Core.scala 119:23]
node _br_target_T_2 = tail(_br_target_T_1, 1) @[src/main/scala/sicore/Core.scala 119:23]
node br_target = bits(_br_target_T_2, 31, 0) @[src/main/scala/sicore/Core.scala 119:13 24:23]
node pc_next = mux(br_flg, br_target, _pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node rd_addr = bits(io_imem_inst, 15, 11) @[src/main/scala/sicore/Core.scala 41:21]
node _csignals_T_87 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_88 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_89 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_90 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_91 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_92 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_93 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_94 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_95 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_96 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_97 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_98 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_99 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_100 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_101 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_102 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_103 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_3 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_104 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_105 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_106 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_107 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_108 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_109 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_110 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_111 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_112 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_113 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_114 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_115 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_116 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_117 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_118 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_119 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_120 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_121 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_122 = mux(_csignals_T_33, UInt<3>("h3"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_123 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_124 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_125 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_126 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_127 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_128 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_129 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_130 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_131 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_132 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_133 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_134 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_135 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_136 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _csignals_T_137 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
node _wb_data_T = eq(csignals_5, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 130:15]
node _wb_data_T_1 = eq(csignals_5, UInt<3>("h3")) @[src/main/scala/sicore/Core.scala 131:15]
node _wb_data_T_2 = mux(_wb_data_T_1, pc_plus4, alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node wb_data = mux(_wb_data_T, io_dmem_rdata, _wb_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16]
node _T = eq(csignals_4, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 136:15]
node _T_1 = neq(rd_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 136:36]
node _T_2 = and(_T, _T_1) @[src/main/scala/sicore/Core.scala 136:25]
node _GEN_0 = validif(_T_2, rd_addr) @[src/main/scala/sicore/Core.scala 136:45 137:12]
node _GEN_1 = validif(_T_2, clock) @[src/main/scala/sicore/Core.scala 136:45 137:12]
node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 136:45 137:12 16:20]
node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/sicore/Core.scala 136:45 137:22]
node _GEN_4 = validif(_T_2, wb_data) @[src/main/scala/sicore/Core.scala 136:45 137:22]
node _io_exit_T = eq(io_imem_inst, UInt<32>("h114514")) @[src/main/scala/sicore/Core.scala 140:20]
node _T_3 = asUInt(reset) @[src/main/scala/sicore/Core.scala 143:9]
node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 143:9]
node _T_5 = asUInt(reset) @[src/main/scala/sicore/Core.scala 144:9]
node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 144:9]
node _T_7 = asUInt(reset) @[src/main/scala/sicore/Core.scala 145:9]
node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 145:9]
node _T_9 = asUInt(reset) @[src/main/scala/sicore/Core.scala 146:9]
node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 146:9]
node _T_11 = asUInt(reset) @[src/main/scala/sicore/Core.scala 147:9]
node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 147:9]
node _T_13 = asUInt(reset) @[src/main/scala/sicore/Core.scala 148:9]
node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 148:9]
node _T_15 = asUInt(reset) @[src/main/scala/sicore/Core.scala 149:9]
node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 149:9]
node _T_17 = asUInt(reset) @[src/main/scala/sicore/Core.scala 150:9]
node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 150:9]
io_imem_addr <= pc_reg @[src/main/scala/sicore/Core.scala 20:16]
io_dmem_addr <= alu_out @[src/main/scala/sicore/Core.scala 122:16]
io_dmem_wen <= bits(csignals_3, 0, 0) @[src/main/scala/sicore/Core.scala 123:15]
io_dmem_wdata <= rt_data @[src/main/scala/sicore/Core.scala 124:17]
io_exit <= _io_exit_T @[src/main/scala/sicore/Core.scala 140:11]
regfile.rs_data_MPORT.addr <= rs_addr @[src/main/scala/sicore/Core.scala 42:47]
regfile.rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 42:47]
regfile.rs_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 42:47]
regfile.rt_data_MPORT.addr <= rt_addr @[src/main/scala/sicore/Core.scala 43:47]
regfile.rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 43:47]
regfile.rt_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 43:47]
regfile.MPORT.addr <= _GEN_0
regfile.MPORT.en <= _GEN_2
regfile.MPORT.clk <= _GEN_1
regfile.MPORT.data <= _GEN_4
regfile.MPORT.mask <= _GEN_3
pc_reg <= mux(reset, UInt<32>("h0"), pc_next) @[src/main/scala/sicore/Core.scala 19:{23,23} 36:10]
printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/sicore/Core.scala 143:9]
printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "io.pc: 0x%x\ninst: 0x%x \n", pc_reg, io_imem_inst) : printf_1 @[src/main/scala/sicore/Core.scala 144:9]
printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "pc_next: 0x%x\n", pc_next) : printf_2 @[src/main/scala/sicore/Core.scala 145:9]
printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "rs_addr: 0x%x\n", rs_addr) : printf_3 @[src/main/scala/sicore/Core.scala 146:9]
printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "rd_addr: 0x%x\n", rd_addr) : printf_4 @[src/main/scala/sicore/Core.scala 147:9]
printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "rs_data: 0x%x\n", rs_data) : printf_5 @[src/main/scala/sicore/Core.scala 148:9]
printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "wb_data: 0x%x\n", wb_data) : printf_6 @[src/main/scala/sicore/Core.scala 149:9]
printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "---------------\n") : printf_7 @[src/main/scala/sicore/Core.scala 150:9]
module Memory : @[src/main/scala/sicore/Memory.scala 24:7]
input clock : Clock @[src/main/scala/sicore/Memory.scala 24:7]
input reset : UInt<1> @[src/main/scala/sicore/Memory.scala 24:7]
input io_imem_addr : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14]
output io_imem_inst : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14]
input io_dmem_addr : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14]
output io_dmem_rdata : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14]
input io_dmem_wen : UInt<1> @[src/main/scala/sicore/Memory.scala 25:14]
input io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14]
mem mem : @[src/main/scala/sicore/Memory.scala 31:16]
data-type => UInt<8>
depth => 4096
read-latency => 0
write-latency => 1
reader => io_imem_inst_MPORT
reader => io_imem_inst_MPORT_1
reader => io_imem_inst_MPORT_2
reader => io_imem_inst_MPORT_3
reader => io_dmem_rdata_MPORT
reader => io_dmem_rdata_MPORT_1
reader => io_dmem_rdata_MPORT_2
reader => io_dmem_rdata_MPORT_3
writer => MPORT
writer => MPORT_1
writer => MPORT_2
writer => MPORT_3
read-under-write => undefined
node _io_imem_inst_T = add(io_imem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 38:22]
node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[src/main/scala/sicore/Memory.scala 38:22]
node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 11, 0) @[src/main/scala/sicore/Memory.scala 38:8]
node _io_imem_inst_T_3 = add(io_imem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 39:22]
node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[src/main/scala/sicore/Memory.scala 39:22]
node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 11, 0) @[src/main/scala/sicore/Memory.scala 39:8]
node _io_imem_inst_T_6 = add(io_imem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 40:22]
node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[src/main/scala/sicore/Memory.scala 40:22]
node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 40:8]
node _io_imem_inst_T_9 = bits(io_imem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 41:8]
node io_imem_inst_lo = cat(mem.io_imem_inst_MPORT_2.data, mem.io_imem_inst_MPORT_3.data) @[src/main/scala/sicore/Memory.scala 37:22]
node io_imem_inst_hi = cat(mem.io_imem_inst_MPORT.data, mem.io_imem_inst_MPORT_1.data) @[src/main/scala/sicore/Memory.scala 37:22]
node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[src/main/scala/sicore/Memory.scala 37:22]
node _io_dmem_rdata_T = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 46:22]
node _io_dmem_rdata_T_1 = tail(_io_dmem_rdata_T, 1) @[src/main/scala/sicore/Memory.scala 46:22]
node _io_dmem_rdata_T_2 = bits(_io_dmem_rdata_T_1, 11, 0) @[src/main/scala/sicore/Memory.scala 46:8]
node _io_dmem_rdata_T_3 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 47:22]
node _io_dmem_rdata_T_4 = tail(_io_dmem_rdata_T_3, 1) @[src/main/scala/sicore/Memory.scala 47:22]
node _io_dmem_rdata_T_5 = bits(_io_dmem_rdata_T_4, 11, 0) @[src/main/scala/sicore/Memory.scala 47:8]
node _io_dmem_rdata_T_6 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 48:22]
node _io_dmem_rdata_T_7 = tail(_io_dmem_rdata_T_6, 1) @[src/main/scala/sicore/Memory.scala 48:22]
node _io_dmem_rdata_T_8 = bits(_io_dmem_rdata_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 48:8]
node _io_dmem_rdata_T_9 = bits(io_dmem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 49:8]
node io_dmem_rdata_lo = cat(mem.io_dmem_rdata_MPORT_2.data, mem.io_dmem_rdata_MPORT_3.data) @[src/main/scala/sicore/Memory.scala 45:23]
node io_dmem_rdata_hi = cat(mem.io_dmem_rdata_MPORT.data, mem.io_dmem_rdata_MPORT_1.data) @[src/main/scala/sicore/Memory.scala 45:23]
node _io_dmem_rdata_T_10 = cat(io_dmem_rdata_hi, io_dmem_rdata_lo) @[src/main/scala/sicore/Memory.scala 45:23]
node _T = bits(io_dmem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 54:8]
node _T_1 = bits(io_dmem_wdata, 7, 0) @[src/main/scala/sicore/Memory.scala 54:39]
node _T_2 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 55:22]
node _T_3 = tail(_T_2, 1) @[src/main/scala/sicore/Memory.scala 55:22]
node _T_4 = bits(_T_3, 11, 0) @[src/main/scala/sicore/Memory.scala 55:8]
node _T_5 = bits(io_dmem_wdata, 15, 8) @[src/main/scala/sicore/Memory.scala 55:57]
node _T_6 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 56:22]
node _T_7 = tail(_T_6, 1) @[src/main/scala/sicore/Memory.scala 56:22]
node _T_8 = bits(_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 56:8]
node _T_9 = bits(io_dmem_wdata, 23, 16) @[src/main/scala/sicore/Memory.scala 56:57]
node _T_10 = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 57:22]
node _T_11 = tail(_T_10, 1) @[src/main/scala/sicore/Memory.scala 57:22]
node _T_12 = bits(_T_11, 11, 0) @[src/main/scala/sicore/Memory.scala 57:8]
node _T_13 = bits(io_dmem_wdata, 31, 24) @[src/main/scala/sicore/Memory.scala 57:57]
node _GEN_0 = validif(io_dmem_wen, _T) @[src/main/scala/sicore/Memory.scala 53:21 54:8]
node _GEN_1 = validif(io_dmem_wen, clock) @[src/main/scala/sicore/Memory.scala 53:21 54:8]
node _GEN_2 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Memory.scala 31:16 53:21 54:8]
node _GEN_3 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/sicore/Memory.scala 53:21 54:23]
node _GEN_4 = validif(io_dmem_wen, _T_1) @[src/main/scala/sicore/Memory.scala 53:21 54:23]
node _GEN_5 = validif(io_dmem_wen, _T_4) @[src/main/scala/sicore/Memory.scala 53:21 55:8]
node _GEN_6 = validif(io_dmem_wen, _T_5) @[src/main/scala/sicore/Memory.scala 53:21 55:41]
node _GEN_7 = validif(io_dmem_wen, _T_8) @[src/main/scala/sicore/Memory.scala 53:21 56:8]
node _GEN_8 = validif(io_dmem_wen, _T_9) @[src/main/scala/sicore/Memory.scala 53:21 56:41]
node _GEN_9 = validif(io_dmem_wen, _T_12) @[src/main/scala/sicore/Memory.scala 53:21 57:8]
node _GEN_10 = validif(io_dmem_wen, _T_13) @[src/main/scala/sicore/Memory.scala 53:21 57:41]
io_imem_inst <= _io_imem_inst_T_10 @[src/main/scala/sicore/Memory.scala 37:16]
io_dmem_rdata <= _io_dmem_rdata_T_10 @[src/main/scala/sicore/Memory.scala 45:17]
mem.io_imem_inst_MPORT.addr <= _io_imem_inst_T_2 @[src/main/scala/sicore/Memory.scala 38:8]
mem.io_imem_inst_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 38:8]
mem.io_imem_inst_MPORT.clk <= clock @[src/main/scala/sicore/Memory.scala 38:8]
mem.io_imem_inst_MPORT_1.addr <= _io_imem_inst_T_5 @[src/main/scala/sicore/Memory.scala 39:8]
mem.io_imem_inst_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 39:8]
mem.io_imem_inst_MPORT_1.clk <= clock @[src/main/scala/sicore/Memory.scala 39:8]
mem.io_imem_inst_MPORT_2.addr <= _io_imem_inst_T_8 @[src/main/scala/sicore/Memory.scala 40:8]
mem.io_imem_inst_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 40:8]
mem.io_imem_inst_MPORT_2.clk <= clock @[src/main/scala/sicore/Memory.scala 40:8]
mem.io_imem_inst_MPORT_3.addr <= _io_imem_inst_T_9 @[src/main/scala/sicore/Memory.scala 41:8]
mem.io_imem_inst_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 41:8]
mem.io_imem_inst_MPORT_3.clk <= clock @[src/main/scala/sicore/Memory.scala 41:8]
mem.io_dmem_rdata_MPORT.addr <= _io_dmem_rdata_T_2 @[src/main/scala/sicore/Memory.scala 46:8]
mem.io_dmem_rdata_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 46:8]
mem.io_dmem_rdata_MPORT.clk <= clock @[src/main/scala/sicore/Memory.scala 46:8]
mem.io_dmem_rdata_MPORT_1.addr <= _io_dmem_rdata_T_5 @[src/main/scala/sicore/Memory.scala 47:8]
mem.io_dmem_rdata_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 47:8]
mem.io_dmem_rdata_MPORT_1.clk <= clock @[src/main/scala/sicore/Memory.scala 47:8]
mem.io_dmem_rdata_MPORT_2.addr <= _io_dmem_rdata_T_8 @[src/main/scala/sicore/Memory.scala 48:8]
mem.io_dmem_rdata_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 48:8]
mem.io_dmem_rdata_MPORT_2.clk <= clock @[src/main/scala/sicore/Memory.scala 48:8]
mem.io_dmem_rdata_MPORT_3.addr <= _io_dmem_rdata_T_9 @[src/main/scala/sicore/Memory.scala 49:8]
mem.io_dmem_rdata_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 49:8]
mem.io_dmem_rdata_MPORT_3.clk <= clock @[src/main/scala/sicore/Memory.scala 49:8]
mem.MPORT.addr <= _GEN_0
mem.MPORT.en <= _GEN_2
mem.MPORT.clk <= _GEN_1
mem.MPORT.data <= _GEN_4
mem.MPORT.mask <= _GEN_3
mem.MPORT_1.addr <= _GEN_5
mem.MPORT_1.en <= _GEN_2
mem.MPORT_1.clk <= _GEN_1
mem.MPORT_1.data <= _GEN_6
mem.MPORT_1.mask <= _GEN_3
mem.MPORT_2.addr <= _GEN_7
mem.MPORT_2.en <= _GEN_2
mem.MPORT_2.clk <= _GEN_1
mem.MPORT_2.data <= _GEN_8
mem.MPORT_2.mask <= _GEN_3
mem.MPORT_3.addr <= _GEN_9
mem.MPORT_3.en <= _GEN_2
mem.MPORT_3.clk <= _GEN_1
mem.MPORT_3.data <= _GEN_10
mem.MPORT_3.mask <= _GEN_3
module TopOrigin : @[src/main/scala/sicore/Top.scala 8:7]
input clock : Clock @[src/main/scala/sicore/Top.scala 8:7]
input reset : UInt<1> @[src/main/scala/sicore/Top.scala 8:7]
output io_exit : UInt<1> @[src/main/scala/sicore/Top.scala 9:14]
inst core of Core @[src/main/scala/sicore/Top.scala 12:20]
inst memory of Memory @[src/main/scala/sicore/Top.scala 13:22]
io_exit <= core.io_exit @[src/main/scala/sicore/Top.scala 16:11]
core.clock <= clock
core.reset <= reset
core.io_imem_inst <= memory.io_imem_inst @[src/main/scala/sicore/Top.scala 14:16]
core.io_dmem_rdata <= memory.io_dmem_rdata @[src/main/scala/sicore/Top.scala 15:16]
memory.clock <= clock
memory.reset <= reset
memory.io_imem_addr <= core.io_imem_addr @[src/main/scala/sicore/Top.scala 14:16]
memory.io_dmem_addr <= core.io_dmem_addr @[src/main/scala/sicore/Top.scala 15:16]
memory.io_dmem_wen <= core.io_dmem_wen @[src/main/scala/sicore/Top.scala 15:16]
memory.io_dmem_wdata <= core.io_dmem_wdata @[src/main/scala/sicore/Top.scala 15:16]