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Code Optimization and Clean Up

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CGH0S7
2025-01-02 17:12:14 +08:00
parent 106519d1ab
commit b4e64b8f52
168 changed files with 689 additions and 1079 deletions
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52
Regfile.sv
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@ -18,32 +18,33 @@
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module regfile_32x32(
input [4:0] R0_addr,
input R0_en,
R0_clk,
output [31:0] R0_data,
input [4:0] R1_addr,
input R1_en,
R1_clk,
output [31:0] R1_data,
input [4:0] W0_addr,
input W0_en,
W0_clk,
output [3:0] io_anodes,
output [6:0] io_segments,
input [31:0] W0_data
);
reg [31:0] Memory[0:31];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
wire [31:0] reg16_value = Memory[16];
DynamicDisplay display (
module regfile_32x32(
input [4:0] R0_addr,
input R0_en,
R0_clk,
output [31:0] R0_data,
input [4:0] R1_addr,
input R1_en,
R1_clk,
output [31:0] R1_data,
input [4:0] W0_addr,
input W0_en,
W0_clk,
output [3:0] io_anodes,
output [6:0] io_segments,
input [31:0] W0_data
);
reg [31:0] Memory[0:31];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
wire [31:0] reg16_value = Memory[16];
DynamicDisplay display (
.clock (W0_clk),
.reset (1'b0),
.reg_result (reg16_value),
@ -51,4 +52,3 @@ module regfile_32x32(
.io_segments (io_segments)
);
endmodule