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Code Optimization and Clean Up

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CGH0S7
2025-01-02 17:12:14 +08:00
parent 106519d1ab
commit b4e64b8f52
168 changed files with 689 additions and 1079 deletions
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2
.gitignore vendored
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@ -8,6 +8,8 @@
*.code-workspace *.code-workspace
target/* target/*
.vscode .vscode
test_run_dir
target
# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
hs_err_pid* hs_err_pid*

800
Core.sv
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@ -20,408 +20,408 @@
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
module Core( module Core(
input clock, input clock,
reset, reset,
output [31:0] io_imem_addr, output [31:0] io_imem_addr,
input [31:0] io_imem_inst, input [31:0] io_imem_inst,
output [31:0] io_dmem_addr, output [31:0] io_dmem_addr,
input [31:0] io_dmem_rdata, input [31:0] io_dmem_rdata,
output io_dmem_wen, output io_dmem_wen,
output [31:0] io_dmem_wdata, output [31:0] io_dmem_wdata,
output [3:0] io_anodes, output [3:0] io_anodes,
output [6:0] io_segments, output [6:0] io_segments,
output io_exit output io_exit
); );
wire exe_jmp_flg; wire exe_jmp_flg;
wire exe_br_flg; wire exe_br_flg;
wire [31:0] _regfile_ext_R0_data; wire [31:0] _regfile_ext_R0_data;
wire [31:0] _regfile_ext_R1_data; wire [31:0] _regfile_ext_R1_data;
reg [31:0] id_reg_pc; reg [31:0] id_reg_pc;
reg [31:0] id_reg_inst; reg [31:0] id_reg_inst;
reg [31:0] exe_reg_pc; reg [31:0] exe_reg_pc;
reg [4:0] exe_reg_wb_addr; reg [4:0] exe_reg_wb_addr;
reg [31:0] exe_reg_op1_data; reg [31:0] exe_reg_op1_data;
reg [31:0] exe_reg_op2_data; reg [31:0] exe_reg_op2_data;
reg [31:0] exe_reg_rt_data; reg [31:0] exe_reg_rt_data;
reg [4:0] exe_reg_exe_fun; reg [4:0] exe_reg_exe_fun;
reg [1:0] exe_reg_mem_wen; reg [1:0] exe_reg_mem_wen;
reg [1:0] exe_reg_rf_wen; reg [1:0] exe_reg_rf_wen;
reg [2:0] exe_reg_wb_sel; reg [2:0] exe_reg_wb_sel;
reg [31:0] exe_reg_imm_i_sext; reg [31:0] exe_reg_imm_i_sext;
reg [31:0] mem_reg_pc; reg [31:0] mem_reg_pc;
reg [4:0] mem_reg_wb_addr; reg [4:0] mem_reg_wb_addr;
reg [31:0] mem_reg_rt_data; reg [31:0] mem_reg_rt_data;
reg [1:0] mem_reg_mem_wen; reg [1:0] mem_reg_mem_wen;
reg [1:0] mem_reg_rf_wen; reg [1:0] mem_reg_rf_wen;
reg [2:0] mem_reg_wb_sel; reg [2:0] mem_reg_wb_sel;
reg [31:0] mem_reg_alu_out; reg [31:0] mem_reg_alu_out;
reg [4:0] wb_reg_wb_addr; reg [4:0] wb_reg_wb_addr;
reg [1:0] wb_reg_rf_wen; reg [1:0] wb_reg_rf_wen;
reg [31:0] wb_reg_wb_data; reg [31:0] wb_reg_wb_data;
reg [31:0] if_reg_pc; reg [31:0] if_reg_pc;
wire _id_inst_T = exe_br_flg | exe_jmp_flg; wire _id_inst_T = exe_br_flg | exe_jmp_flg;
wire _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1; wire _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
wire stall_flg = wire stall_flg =
_id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr _id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
| _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr; | _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst; wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
wire _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1; wire _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
wire _exe_alu_out_T = exe_reg_exe_fun == 5'h1; wire _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data; wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
wire _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2; wire _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data; wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
wire _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3; wire _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data; wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
wire _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4; wire _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data; wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
wire _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5; wire _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data; wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
wire _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6; wire _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0]; wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
wire _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7; wire _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]}; wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN; wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
wire _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8; wire _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN); wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
wire _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9; wire _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
wire _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD; wire _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0; wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}; wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
wire [31:0] exe_alu_out = wire [31:0] exe_alu_out =
_exe_alu_out_T _exe_alu_out_T
? _exe_alu_out_T_1 ? _exe_alu_out_T_1
: _exe_alu_out_T_3 : _exe_alu_out_T_3
? _exe_alu_out_T_4 ? _exe_alu_out_T_4
: _exe_alu_out_T_6 : _exe_alu_out_T_6
? _exe_alu_out_T_7 ? _exe_alu_out_T_7
: _exe_alu_out_T_8 : _exe_alu_out_T_8
? _exe_alu_out_T_9 ? _exe_alu_out_T_9
: _exe_alu_out_T_10 : _exe_alu_out_T_10
? _exe_alu_out_T_11 ? _exe_alu_out_T_11
: _exe_alu_out_T_12 : _exe_alu_out_T_12
? _exe_alu_out_T_14[31:0] ? _exe_alu_out_T_14[31:0]
: _exe_alu_out_T_16 : _exe_alu_out_T_16
? _exe_alu_out_T_18 ? _exe_alu_out_T_18
: _exe_alu_out_T_19 : _exe_alu_out_T_19
? _exe_alu_out_T_22 ? _exe_alu_out_T_22
: _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29; : _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
assign exe_br_flg = assign exe_br_flg =
exe_reg_exe_fun == 5'hB exe_reg_exe_fun == 5'hB
? exe_reg_op1_data == exe_reg_op2_data ? exe_reg_op1_data == exe_reg_op2_data
: exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data; : exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
assign exe_jmp_flg = exe_reg_wb_sel == 3'h3; assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
wire [31:0] mem_wb_data = wire [31:0] mem_wb_data =
mem_reg_wb_sel == 3'h2 mem_reg_wb_sel == 3'h2
? io_dmem_rdata ? io_dmem_rdata
: mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out; : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
always @(posedge clock) begin always @(posedge clock) begin
if (reset) begin if (reset) begin
id_reg_pc <= 32'h0; id_reg_pc <= 32'h0;
id_reg_inst <= 32'h0; id_reg_inst <= 32'h0;
exe_reg_pc <= 32'h0; exe_reg_pc <= 32'h0;
exe_reg_wb_addr <= 5'h0; exe_reg_wb_addr <= 5'h0;
exe_reg_op1_data <= 32'h0;
exe_reg_op2_data <= 32'h0;
exe_reg_rt_data <= 32'h0;
exe_reg_exe_fun <= 5'h0;
exe_reg_mem_wen <= 2'h0;
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
exe_reg_imm_i_sext <= 32'h0;
mem_reg_pc <= 32'h0;
mem_reg_wb_addr <= 5'h0;
mem_reg_rt_data <= 32'h0;
mem_reg_mem_wen <= 2'h0;
mem_reg_rf_wen <= 2'h0;
mem_reg_wb_sel <= 3'h0;
mem_reg_alu_out <= 32'h0;
wb_reg_wb_addr <= 5'h0;
wb_reg_rf_wen <= 2'h0;
wb_reg_wb_data <= 32'h0;
if_reg_pc <= 32'h0;
end
else begin
automatic logic _id_rt_data_T_5;
automatic logic _id_rt_data_T;
automatic logic _id_rt_data_T_3;
automatic logic _id_rt_data_T_6;
automatic logic _id_rt_data_T_9;
automatic logic [31:0] id_imm_i_sext;
automatic logic _csignals_T_1 = id_inst[31:26] == 6'h23;
automatic logic _csignals_T_3;
automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
automatic logic _csignals_T_5 = _GEN_1 == 12'h20;
automatic logic _csignals_T_7 = id_inst[31:26] == 6'h8;
automatic logic _csignals_T_9;
automatic logic _csignals_T_11;
automatic logic _csignals_T_13;
automatic logic _csignals_T_15;
automatic logic _csignals_T_17;
automatic logic _csignals_T_19;
automatic logic _csignals_T_21;
automatic logic _csignals_T_23;
automatic logic _csignals_T_25;
automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
automatic logic _csignals_T_27;
automatic logic _csignals_T_29;
automatic logic _csignals_T_31;
automatic logic _csignals_T_33;
automatic logic _csignals_T_35;
automatic logic _GEN_3;
automatic logic _GEN_4;
automatic logic [1:0] csignals_1;
automatic logic [2:0] csignals_2;
automatic logic _GEN_5;
automatic logic _GEN_6;
_id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
_id_rt_data_T = id_inst[20:16] == 5'h0;
_id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
_id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
_id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
_csignals_T_3 = id_inst[31:26] == 6'h2B;
_csignals_T_9 = _GEN_1 == 12'h22;
_csignals_T_11 = _GEN_1 == 12'h24;
_csignals_T_13 = _GEN_1 == 12'h25;
_csignals_T_15 = _GEN_1 == 12'h26;
_csignals_T_17 = id_inst[31:26] == 6'hC;
_csignals_T_19 = id_inst[31:26] == 6'hD;
_csignals_T_21 = _GEN_1 == 12'h2A;
_csignals_T_23 = id_inst[31:26] == 6'h4;
_csignals_T_25 = id_inst[31:26] == 6'h5;
_csignals_T_27 = _GEN_2 == 17'h0;
_csignals_T_29 = _GEN_2 == 17'h2;
_csignals_T_31 = _GEN_2 == 17'h3;
_csignals_T_33 = id_inst[31:26] == 6'h3;
_csignals_T_35 = _GEN_1 == 12'h8;
_GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
_GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
csignals_1 =
_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
| _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
| _csignals_T_19 | _GEN_4 | ~_csignals_T_33
? 2'h1
: 2'h2;
csignals_2 =
_csignals_T_1 | _csignals_T_3
? 3'h2
: _csignals_T_5
? 3'h1
: _csignals_T_7
? 3'h2
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
? 3'h1
: _csignals_T_17 | _csignals_T_19
? 3'h2
: _GEN_4
? 3'h1
: _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
_GEN_5 = _csignals_T_23 | _csignals_T_25;
_GEN_6 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
if (~stall_flg)
id_reg_pc <= if_reg_pc;
if (_id_inst_T)
id_reg_inst <= 32'h20000000;
else if (~stall_flg)
id_reg_inst <= io_imem_inst;
exe_reg_pc <= id_reg_pc;
if ((_csignals_T_1
? 3'h2
: _csignals_T_3
? 3'h0
: _GEN_6
? 3'h1
: _GEN_5
? 3'h0
: _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
& id_inst[31:26] == 6'h0)
exe_reg_wb_addr <= id_inst[15:11];
else if (id_inst[31:26] == 6'h3)
exe_reg_wb_addr <= 5'h1F;
else
exe_reg_wb_addr <= id_inst[20:16];
if (csignals_1 == 2'h1) begin
if (id_inst[25:21] == 5'h0)
exe_reg_op1_data <= 32'h0;
else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
if (_exe_alu_out_T)
exe_reg_op1_data <= _exe_alu_out_T_1;
else if (_exe_alu_out_T_3)
exe_reg_op1_data <= _exe_alu_out_T_4;
else if (_exe_alu_out_T_6)
exe_reg_op1_data <= _exe_alu_out_T_7;
else if (_exe_alu_out_T_8)
exe_reg_op1_data <= _exe_alu_out_T_9;
else if (_exe_alu_out_T_10)
exe_reg_op1_data <= _exe_alu_out_T_11;
else if (_exe_alu_out_T_12)
exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
else if (_exe_alu_out_T_16)
exe_reg_op1_data <= _exe_alu_out_T_18;
else if (_exe_alu_out_T_19)
exe_reg_op1_data <= _exe_alu_out_T_22;
else if (_exe_alu_out_T_24)
exe_reg_op1_data <= _GEN_0;
else if (~_exe_alu_out_T_28)
exe_reg_op1_data <= 32'h0; exe_reg_op1_data <= 32'h0;
exe_reg_op2_data <= 32'h0;
exe_reg_rt_data <= 32'h0;
exe_reg_exe_fun <= 5'h0;
exe_reg_mem_wen <= 2'h0;
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
exe_reg_imm_i_sext <= 32'h0;
mem_reg_pc <= 32'h0;
mem_reg_wb_addr <= 5'h0;
mem_reg_rt_data <= 32'h0;
mem_reg_mem_wen <= 2'h0;
mem_reg_rf_wen <= 2'h0;
mem_reg_wb_sel <= 3'h0;
mem_reg_alu_out <= 32'h0;
wb_reg_wb_addr <= 5'h0;
wb_reg_rf_wen <= 2'h0;
wb_reg_wb_data <= 32'h0;
if_reg_pc <= 32'h0;
end end
else begin else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
automatic logic _id_rt_data_T_5; exe_reg_op1_data <= mem_wb_data;
automatic logic _id_rt_data_T; else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
automatic logic _id_rt_data_T_3; exe_reg_op1_data <= wb_reg_wb_data;
automatic logic _id_rt_data_T_6; else
automatic logic _id_rt_data_T_9; exe_reg_op1_data <= _regfile_ext_R1_data;
automatic logic [31:0] id_imm_i_sext; end
automatic logic _csignals_T_1 = id_inst[31:26] == 6'h23; else if (csignals_1 == 2'h2)
automatic logic _csignals_T_3; exe_reg_op1_data <= id_reg_pc;
automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]}; else
automatic logic _csignals_T_5 = _GEN_1 == 12'h20; exe_reg_op1_data <= 32'h0;
automatic logic _csignals_T_7 = id_inst[31:26] == 6'h8; if (csignals_2 == 3'h1) begin
automatic logic _csignals_T_9; if (_id_rt_data_T)
automatic logic _csignals_T_11; exe_reg_op2_data <= 32'h0;
automatic logic _csignals_T_13; else if (_id_rt_data_T_3) begin
automatic logic _csignals_T_15; if (_exe_alu_out_T)
automatic logic _csignals_T_17; exe_reg_op2_data <= _exe_alu_out_T_1;
automatic logic _csignals_T_19; else if (_exe_alu_out_T_3)
automatic logic _csignals_T_21; exe_reg_op2_data <= _exe_alu_out_T_4;
automatic logic _csignals_T_23; else if (_exe_alu_out_T_6)
automatic logic _csignals_T_25; exe_reg_op2_data <= _exe_alu_out_T_7;
automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]}; else if (_exe_alu_out_T_8)
automatic logic _csignals_T_27; exe_reg_op2_data <= _exe_alu_out_T_9;
automatic logic _csignals_T_29; else if (_exe_alu_out_T_10)
automatic logic _csignals_T_31; exe_reg_op2_data <= _exe_alu_out_T_11;
automatic logic _csignals_T_33; else if (_exe_alu_out_T_12)
automatic logic _csignals_T_35; exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
automatic logic _GEN_3; else if (_exe_alu_out_T_16)
automatic logic _GEN_4; exe_reg_op2_data <= _exe_alu_out_T_18;
automatic logic [1:0] csignals_1; else if (_exe_alu_out_T_19)
automatic logic [2:0] csignals_2; exe_reg_op2_data <= _exe_alu_out_T_22;
automatic logic _GEN_5; else if (_exe_alu_out_T_24)
automatic logic _GEN_6; exe_reg_op2_data <= _GEN_0;
_id_rt_data_T_5 = mem_reg_rf_wen == 2'h1; else
_id_rt_data_T = id_inst[20:16] == 5'h0; exe_reg_op2_data <= _exe_alu_out_T_29;
_id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
_id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
_id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
_csignals_T_3 = id_inst[31:26] == 6'h2B;
_csignals_T_9 = _GEN_1 == 12'h22;
_csignals_T_11 = _GEN_1 == 12'h24;
_csignals_T_13 = _GEN_1 == 12'h25;
_csignals_T_15 = _GEN_1 == 12'h26;
_csignals_T_17 = id_inst[31:26] == 6'hC;
_csignals_T_19 = id_inst[31:26] == 6'hD;
_csignals_T_21 = _GEN_1 == 12'h2A;
_csignals_T_23 = id_inst[31:26] == 6'h4;
_csignals_T_25 = id_inst[31:26] == 6'h5;
_csignals_T_27 = _GEN_2 == 17'h0;
_csignals_T_29 = _GEN_2 == 17'h2;
_csignals_T_31 = _GEN_2 == 17'h3;
_csignals_T_33 = id_inst[31:26] == 6'h3;
_csignals_T_35 = _GEN_1 == 12'h8;
_GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
_GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
csignals_1 =
_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
| _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
| _csignals_T_19 | _GEN_4 | ~_csignals_T_33
? 2'h1
: 2'h2;
csignals_2 =
_csignals_T_1 | _csignals_T_3
? 3'h2
: _csignals_T_5
? 3'h1
: _csignals_T_7
? 3'h2
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
? 3'h1
: _csignals_T_17 | _csignals_T_19
? 3'h2
: _GEN_4
? 3'h1
: _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
_GEN_5 = _csignals_T_23 | _csignals_T_25;
_GEN_6 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
if (~stall_flg)
id_reg_pc <= if_reg_pc;
if (_id_inst_T)
id_reg_inst <= 32'h20000000;
else if (~stall_flg)
id_reg_inst <= io_imem_inst;
exe_reg_pc <= id_reg_pc;
if ((_csignals_T_1
? 3'h2
: _csignals_T_3
? 3'h0
: _GEN_6
? 3'h1
: _GEN_5
? 3'h0
: _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
& id_inst[31:26] == 6'h0)
exe_reg_wb_addr <= id_inst[15:11];
else if (id_inst[31:26] == 6'h3)
exe_reg_wb_addr <= 5'h1F;
else
exe_reg_wb_addr <= id_inst[20:16];
if (csignals_1 == 2'h1) begin
if (id_inst[25:21] == 5'h0)
exe_reg_op1_data <= 32'h0;
else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
if (_exe_alu_out_T)
exe_reg_op1_data <= _exe_alu_out_T_1;
else if (_exe_alu_out_T_3)
exe_reg_op1_data <= _exe_alu_out_T_4;
else if (_exe_alu_out_T_6)
exe_reg_op1_data <= _exe_alu_out_T_7;
else if (_exe_alu_out_T_8)
exe_reg_op1_data <= _exe_alu_out_T_9;
else if (_exe_alu_out_T_10)
exe_reg_op1_data <= _exe_alu_out_T_11;
else if (_exe_alu_out_T_12)
exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
else if (_exe_alu_out_T_16)
exe_reg_op1_data <= _exe_alu_out_T_18;
else if (_exe_alu_out_T_19)
exe_reg_op1_data <= _exe_alu_out_T_22;
else if (_exe_alu_out_T_24)
exe_reg_op1_data <= _GEN_0;
else if (~_exe_alu_out_T_28)
exe_reg_op1_data <= 32'h0;
end
else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
exe_reg_op1_data <= mem_wb_data;
else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
exe_reg_op1_data <= wb_reg_wb_data;
else
exe_reg_op1_data <= _regfile_ext_R1_data;
end
else if (csignals_1 == 2'h2)
exe_reg_op1_data <= id_reg_pc;
else
exe_reg_op1_data <= 32'h0;
if (csignals_2 == 3'h1) begin
if (_id_rt_data_T)
exe_reg_op2_data <= 32'h0;
else if (_id_rt_data_T_3) begin
if (_exe_alu_out_T)
exe_reg_op2_data <= _exe_alu_out_T_1;
else if (_exe_alu_out_T_3)
exe_reg_op2_data <= _exe_alu_out_T_4;
else if (_exe_alu_out_T_6)
exe_reg_op2_data <= _exe_alu_out_T_7;
else if (_exe_alu_out_T_8)
exe_reg_op2_data <= _exe_alu_out_T_9;
else if (_exe_alu_out_T_10)
exe_reg_op2_data <= _exe_alu_out_T_11;
else if (_exe_alu_out_T_12)
exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
else if (_exe_alu_out_T_16)
exe_reg_op2_data <= _exe_alu_out_T_18;
else if (_exe_alu_out_T_19)
exe_reg_op2_data <= _exe_alu_out_T_22;
else if (_exe_alu_out_T_24)
exe_reg_op2_data <= _GEN_0;
else
exe_reg_op2_data <= _exe_alu_out_T_29;
end
else if (_id_rt_data_T_6)
exe_reg_op2_data <= mem_wb_data;
else if (_id_rt_data_T_9)
exe_reg_op2_data <= wb_reg_wb_data;
else
exe_reg_op2_data <= _regfile_ext_R0_data;
end
else if (csignals_2 == 3'h2)
exe_reg_op2_data <= id_imm_i_sext;
else if (csignals_2 == 3'h4)
exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
else
exe_reg_op2_data <= 32'h0;
exe_reg_rt_data <=
_id_rt_data_T
? 32'h0
: _id_rt_data_T_3
? exe_alu_out
: _id_rt_data_T_6
? mem_wb_data
: _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_9)
exe_reg_exe_fun <= 5'h2;
else if (_csignals_T_11)
exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_13)
exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_15)
exe_reg_exe_fun <= 5'h5;
else if (_csignals_T_17)
exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_19)
exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_21)
exe_reg_exe_fun <= 5'h9;
else if (_csignals_T_23)
exe_reg_exe_fun <= 5'hB;
else if (_csignals_T_25)
exe_reg_exe_fun <= 5'hC;
else if (_csignals_T_27)
exe_reg_exe_fun <= 5'h6;
else if (_csignals_T_29)
exe_reg_exe_fun <= 5'h7;
else if (_csignals_T_31)
exe_reg_exe_fun <= 5'h8;
else if (_csignals_T_33)
exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_35)
exe_reg_exe_fun <= 5'hD;
else
exe_reg_exe_fun <= 5'h0;
exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
if (_csignals_T_1) begin
exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h2;
end
else if (_csignals_T_3) begin
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
end
else if (_GEN_6) begin
exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h1;
end
else if (_GEN_5) begin
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
end
else begin
exe_reg_rf_wen <=
{1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
if (_GEN_3)
exe_reg_wb_sel <= 3'h1;
else if (_csignals_T_33)
exe_reg_wb_sel <= 3'h3;
else
exe_reg_wb_sel <= 3'h0;
end
exe_reg_imm_i_sext <= id_imm_i_sext;
mem_reg_pc <= exe_reg_pc;
mem_reg_wb_addr <= exe_reg_wb_addr;
mem_reg_rt_data <= exe_reg_rt_data;
mem_reg_mem_wen <= exe_reg_mem_wen;
mem_reg_rf_wen <= exe_reg_rf_wen;
mem_reg_wb_sel <= exe_reg_wb_sel;
mem_reg_alu_out <= exe_alu_out;
wb_reg_wb_addr <= mem_reg_wb_addr;
wb_reg_rf_wen <= mem_reg_rf_wen;
wb_reg_wb_data <= mem_wb_data;
if (exe_br_flg)
if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
else if (exe_jmp_flg)
if_reg_pc <= exe_alu_out;
else if (~stall_flg)
if_reg_pc <= if_reg_pc + 32'h4;
end end
end // always @(posedge) else if (_id_rt_data_T_6)
regfile_32x32 regfile_ext ( exe_reg_op2_data <= mem_wb_data;
.R0_addr (id_inst[20:16]), else if (_id_rt_data_T_9)
.R0_en (1'h1), exe_reg_op2_data <= wb_reg_wb_data;
.R0_clk (clock), else
.R0_data (_regfile_ext_R0_data), exe_reg_op2_data <= _regfile_ext_R0_data;
.R1_addr (id_inst[25:21]), end
.R1_en (1'h1), else if (csignals_2 == 3'h2)
.R1_clk (clock), exe_reg_op2_data <= id_imm_i_sext;
.R1_data (_regfile_ext_R1_data), else if (csignals_2 == 3'h4)
.W0_addr (wb_reg_wb_addr), exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
.W0_en (_id_rt_data_T_8 & (|wb_reg_wb_addr)), else
.W0_clk (clock), exe_reg_op2_data <= 32'h0;
.io_anodes (io_anodes), exe_reg_rt_data <=
.io_segments (io_segments), _id_rt_data_T
.W0_data (wb_reg_wb_data) ? 32'h0
); : _id_rt_data_T_3
assign io_imem_addr = if_reg_pc; ? exe_alu_out
assign io_dmem_addr = mem_reg_alu_out; : _id_rt_data_T_6
assign io_dmem_wen = mem_reg_mem_wen[0]; ? mem_wb_data
assign io_dmem_wdata = mem_reg_rt_data; : _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
assign io_exit = id_reg_inst == 32'h114514; if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_9)
exe_reg_exe_fun <= 5'h2;
else if (_csignals_T_11)
exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_13)
exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_15)
exe_reg_exe_fun <= 5'h5;
else if (_csignals_T_17)
exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_19)
exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_21)
exe_reg_exe_fun <= 5'h9;
else if (_csignals_T_23)
exe_reg_exe_fun <= 5'hB;
else if (_csignals_T_25)
exe_reg_exe_fun <= 5'hC;
else if (_csignals_T_27)
exe_reg_exe_fun <= 5'h6;
else if (_csignals_T_29)
exe_reg_exe_fun <= 5'h7;
else if (_csignals_T_31)
exe_reg_exe_fun <= 5'h8;
else if (_csignals_T_33)
exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_35)
exe_reg_exe_fun <= 5'hD;
else
exe_reg_exe_fun <= 5'h0;
exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
if (_csignals_T_1) begin
exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h2;
end
else if (_csignals_T_3) begin
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
end
else if (_GEN_6) begin
exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h1;
end
else if (_GEN_5) begin
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
end
else begin
exe_reg_rf_wen <=
{1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
if (_GEN_3)
exe_reg_wb_sel <= 3'h1;
else if (_csignals_T_33)
exe_reg_wb_sel <= 3'h3;
else
exe_reg_wb_sel <= 3'h0;
end
exe_reg_imm_i_sext <= id_imm_i_sext;
mem_reg_pc <= exe_reg_pc;
mem_reg_wb_addr <= exe_reg_wb_addr;
mem_reg_rt_data <= exe_reg_rt_data;
mem_reg_mem_wen <= exe_reg_mem_wen;
mem_reg_rf_wen <= exe_reg_rf_wen;
mem_reg_wb_sel <= exe_reg_wb_sel;
mem_reg_alu_out <= exe_alu_out;
wb_reg_wb_addr <= mem_reg_wb_addr;
wb_reg_rf_wen <= mem_reg_rf_wen;
wb_reg_wb_data <= mem_wb_data;
if (exe_br_flg)
if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
else if (exe_jmp_flg)
if_reg_pc <= exe_alu_out;
else if (~stall_flg)
if_reg_pc <= if_reg_pc + 32'h4;
end
end // always @(posedge)
regfile_32x32 regfile_ext (
.R0_addr (id_inst[20:16]),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_regfile_ext_R0_data),
.R1_addr (id_inst[25:21]),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_regfile_ext_R1_data),
.W0_addr (wb_reg_wb_addr),
.W0_en (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
.W0_clk (clock),
.io_anodes (io_anodes),
.io_segments (io_segments),
.W0_data (wb_reg_wb_data)
);
assign io_imem_addr = if_reg_pc;
assign io_dmem_addr = mem_reg_alu_out;
assign io_dmem_wen = mem_reg_mem_wen[0];
assign io_dmem_wdata = mem_reg_rt_data;
assign io_exit = id_reg_inst == 32'h114514;
endmodule endmodule

185
Memory.sv
View File

@ -18,156 +18,43 @@
// Additional Comments: // Additional Comments:
// //
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
module mem_4096x8(
input [11:0] R0_addr,
input R0_en,
R0_clk,
output [7:0] R0_data,
input [11:0] R1_addr,
input R1_en,
R1_clk,
output [7:0] R1_data,
input [11:0] R2_addr,
input R2_en,
R2_clk,
output [7:0] R2_data,
input [11:0] R3_addr,
input R3_en,
R3_clk,
output [7:0] R3_data,
input [11:0] R4_addr,
input R4_en,
R4_clk,
output [7:0] R4_data,
input [11:0] R5_addr,
input R5_en,
R5_clk,
output [7:0] R5_data,
input [11:0] R6_addr,
input R6_en,
R6_clk,
output [7:0] R6_data,
input [11:0] R7_addr,
input R7_en,
R7_clk,
output [7:0] R7_data,
input [11:0] W0_addr,
input W0_en,
W0_clk,
input [7:0] W0_data,
input [11:0] W1_addr,
input W1_en,
W1_clk,
input [7:0] W1_data,
input [11:0] W2_addr,
input W2_en,
W2_clk,
input [7:0] W2_data,
input [11:0] W3_addr,
input W3_en,
W3_clk,
input [7:0] W3_data
);
reg [7:0] Memory[0:4095];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
if (W2_en & 1'h1)
Memory[W2_addr] <= W2_data;
if (W3_en & 1'h1)
Memory[W3_addr] <= W3_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
initial
$readmemh("src/hex/mem.hex", Memory);
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
endmodule
// VCS coverage exclude_file
module Memory( module Memory(
input clock, input clock,
input [31:0] io_imem_addr, input [31:0] io_imem_addr,
output [31:0] io_imem_inst, output [31:0] io_imem_inst,
input [31:0] io_dmem_addr, input [31:0] io_dmem_addr,
output [31:0] io_dmem_rdata, output [31:0] io_dmem_rdata,
input io_dmem_wen, input io_dmem_wen,
input [31:0] io_dmem_wdata input [31:0] io_dmem_wdata
); );
wire [7:0] _mem_ext_R0_data;
wire [7:0] _mem_ext_R1_data; reg [31:0] mem [0:63];
wire [7:0] _mem_ext_R2_data;
wire [7:0] _mem_ext_R3_data;
wire [7:0] _mem_ext_R4_data; initial begin
wire [7:0] _mem_ext_R5_data; mem[0] = 32'h20080001; // addi $t0, $zero, 1
wire [7:0] _mem_ext_R6_data; mem[1] = 32'h20100000; // addi $s0, $zero, 0
wire [7:0] _mem_ext_R7_data; mem[2] = 32'h20120065; // addi $s2, $zero, 101
wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3; mem[3] = 32'h02088020; // add $s0, $s0, $t0
wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2; mem[4] = 32'h21080001; // addi $t0, $t0, 1
wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1; mem[5] = 32'h0112502a; // slt $t2, $t0, $s2
mem_4096x8 mem_ext ( mem[6] = 32'h1540fffc; // bne $t2, $zero, -4
.R0_addr (io_imem_addr[11:0]), mem[7] = 32'h00000000; // nop
.R0_en (1'h1), mem[8] = 32'h00114514; // exit
.R0_clk (clock), end
.R0_data (_mem_ext_R0_data),
.R1_addr (io_imem_addr[11:0] + 12'h1),
.R1_en (1'h1), assign io_imem_inst = mem[io_imem_addr[7:2]];
.R1_clk (clock),
.R1_data (_mem_ext_R1_data), assign io_dmem_rdata = mem[io_dmem_addr[7:2]];
.R2_addr (io_imem_addr[11:0] + 12'h2),
.R2_en (1'h1),
.R2_clk (clock), always @(posedge clock) begin
.R2_data (_mem_ext_R2_data), if (io_dmem_wen) begin
.R3_addr (io_imem_addr[11:0] + 12'h3), mem[io_dmem_addr[7:2]] <= io_dmem_wdata;
.R3_en (1'h1), end
.R3_clk (clock), end
.R3_data (_mem_ext_R3_data),
.R4_addr (io_dmem_addr[11:0]),
.R4_en (1'h1),
.R4_clk (clock),
.R4_data (_mem_ext_R4_data),
.R5_addr (_io_dmem_rdata_T_6),
.R5_en (1'h1),
.R5_clk (clock),
.R5_data (_mem_ext_R5_data),
.R6_addr (_io_dmem_rdata_T_3),
.R6_en (1'h1),
.R6_clk (clock),
.R6_data (_mem_ext_R6_data),
.R7_addr (_io_dmem_rdata_T),
.R7_en (1'h1),
.R7_clk (clock),
.R7_data (_mem_ext_R7_data),
.W0_addr (_io_dmem_rdata_T),
.W0_en (io_dmem_wen),
.W0_clk (clock),
.W0_data (io_dmem_wdata[31:24]),
.W1_addr (_io_dmem_rdata_T_3),
.W1_en (io_dmem_wen),
.W1_clk (clock),
.W1_data (io_dmem_wdata[23:16]),
.W2_addr (_io_dmem_rdata_T_6),
.W2_en (io_dmem_wen),
.W2_clk (clock),
.W2_data (io_dmem_wdata[15:8]),
.W3_addr (io_dmem_addr[11:0]),
.W3_en (io_dmem_wen),
.W3_clk (clock),
.W3_data (io_dmem_wdata[7:0])
);
assign io_imem_inst =
{_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
assign io_dmem_rdata =
{_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
endmodule endmodule

52
Regfile.sv
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@ -18,32 +18,33 @@
// Additional Comments: // Additional Comments:
// //
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
module regfile_32x32(
input [4:0] R0_addr,
input R0_en,
R0_clk,
output [31:0] R0_data,
input [4:0] R1_addr,
input R1_en,
R1_clk,
output [31:0] R1_data,
input [4:0] W0_addr,
input W0_en,
W0_clk,
output [3:0] io_anodes,
output [6:0] io_segments,
input [31:0] W0_data
);
reg [31:0] Memory[0:31]; module regfile_32x32(
always @(posedge W0_clk) begin input [4:0] R0_addr,
if (W0_en & 1'h1) input R0_en,
Memory[W0_addr] <= W0_data; R0_clk,
end // always @(posedge) output [31:0] R0_data,
assign R0_data = R0_en ? Memory[R0_addr] : 32'bx; input [4:0] R1_addr,
assign R1_data = R1_en ? Memory[R1_addr] : 32'bx; input R1_en,
wire [31:0] reg16_value = Memory[16]; R1_clk,
DynamicDisplay display ( output [31:0] R1_data,
input [4:0] W0_addr,
input W0_en,
W0_clk,
output [3:0] io_anodes,
output [6:0] io_segments,
input [31:0] W0_data
);
reg [31:0] Memory[0:31];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
wire [31:0] reg16_value = Memory[16];
DynamicDisplay display (
.clock (W0_clk), .clock (W0_clk),
.reset (1'b0), .reset (1'b0),
.reg_result (reg16_value), .reg_result (reg16_value),
@ -51,4 +52,3 @@ module regfile_32x32(
.io_segments (io_segments) .io_segments (io_segments)
); );
endmodule endmodule

68
Top.sv
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@ -20,39 +20,39 @@
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
module Top( module Top(
input clock, input clock,
reset, reset,
output io_exit, output [3:0] io_anodes,
output [3:0] io_anodes, output [6:0] io_segments,
output [6:0] io_segments output io_exit
); );
wire [31:0] _memory_io_imem_inst; wire [31:0] _memory_io_imem_inst;
wire [31:0] _memory_io_dmem_rdata; wire [31:0] _memory_io_dmem_rdata;
wire [31:0] _core_io_imem_addr; wire [31:0] _core_io_imem_addr;
wire [31:0] _core_io_dmem_addr; wire [31:0] _core_io_dmem_addr;
wire _core_io_dmem_wen; wire _core_io_dmem_wen;
wire [31:0] _core_io_dmem_wdata; wire [31:0] _core_io_dmem_wdata;
Core core ( Core core (
.clock (clock), .clock (clock),
.reset (reset), .reset (reset),
.io_imem_addr (_core_io_imem_addr), .io_imem_addr (_core_io_imem_addr),
.io_imem_inst (_memory_io_imem_inst), .io_imem_inst (_memory_io_imem_inst),
.io_dmem_addr (_core_io_dmem_addr), .io_dmem_addr (_core_io_dmem_addr),
.io_dmem_rdata (_memory_io_dmem_rdata), .io_dmem_rdata (_memory_io_dmem_rdata),
.io_dmem_wen (_core_io_dmem_wen), .io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata), .io_dmem_wdata (_core_io_dmem_wdata),
.io_anodes (io_anodes), .io_anodes (io_anodes),
.io_segments (io_segments), .io_segments (io_segments),
.io_exit (io_exit) .io_exit (io_exit)
); );
Memory memory ( Memory memory (
.clock (clock), .clock (clock),
.io_imem_addr (_core_io_imem_addr), .io_imem_addr (_core_io_imem_addr),
.io_imem_inst (_memory_io_imem_inst), .io_imem_inst (_memory_io_imem_inst),
.io_dmem_addr (_core_io_dmem_addr), .io_dmem_addr (_core_io_dmem_addr),
.io_dmem_rdata (_memory_io_dmem_rdata), .io_dmem_rdata (_memory_io_dmem_rdata),
.io_dmem_wen (_core_io_dmem_wen), .io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata) .io_dmem_wdata (_core_io_dmem_wdata)
); );
endmodule endmodule

135
TopOrigin.sv
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@ -428,80 +428,32 @@ module Core(
endmodule endmodule
// VCS coverage exclude_file // VCS coverage exclude_file
module mem_4096x8( module mem_64x32(
input [11:0] R0_addr, input [5:0] R0_addr,
input R0_en, input R0_en,
R0_clk, R0_clk,
output [7:0] R0_data, output [31:0] R0_data,
input [11:0] R1_addr, input [5:0] R1_addr,
input R1_en, input R1_en,
R1_clk, R1_clk,
output [7:0] R1_data, output [31:0] R1_data,
input [11:0] R2_addr, input [5:0] W0_addr,
input R2_en,
R2_clk,
output [7:0] R2_data,
input [11:0] R3_addr,
input R3_en,
R3_clk,
output [7:0] R3_data,
input [11:0] R4_addr,
input R4_en,
R4_clk,
output [7:0] R4_data,
input [11:0] R5_addr,
input R5_en,
R5_clk,
output [7:0] R5_data,
input [11:0] R6_addr,
input R6_en,
R6_clk,
output [7:0] R6_data,
input [11:0] R7_addr,
input R7_en,
R7_clk,
output [7:0] R7_data,
input [11:0] W0_addr,
input W0_en, input W0_en,
W0_clk, W0_clk,
input [7:0] W0_data, input [31:0] W0_data
input [11:0] W1_addr,
input W1_en,
W1_clk,
input [7:0] W1_data,
input [11:0] W2_addr,
input W2_en,
W2_clk,
input [7:0] W2_data,
input [11:0] W3_addr,
input W3_en,
W3_clk,
input [7:0] W3_data
); );
reg [7:0] Memory[0:4095]; reg [31:0] Memory[0:63];
always @(posedge W0_clk) begin always @(posedge W0_clk) begin
if (W0_en & 1'h1) if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data; Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
if (W2_en & 1'h1)
Memory[W2_addr] <= W2_data;
if (W3_en & 1'h1)
Memory[W3_addr] <= W3_data;
end // always @(posedge) end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_ `ifdef ENABLE_INITIAL_MEM_
initial initial
$readmemh("src/hex/mem.hex", Memory); $readmemh("src/hex/mem.dat", Memory);
`endif // ENABLE_INITIAL_MEM_ `endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 8'bx; assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 8'bx; assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
endmodule endmodule
module Memory( module Memory(
@ -514,71 +466,20 @@ module Memory(
input [31:0] io_dmem_wdata input [31:0] io_dmem_wdata
); );
wire [7:0] _mem_ext_R0_data; mem_64x32 mem_ext (
wire [7:0] _mem_ext_R1_data; .R0_addr (io_imem_addr[7:2]),
wire [7:0] _mem_ext_R2_data;
wire [7:0] _mem_ext_R3_data;
wire [7:0] _mem_ext_R4_data;
wire [7:0] _mem_ext_R5_data;
wire [7:0] _mem_ext_R6_data;
wire [7:0] _mem_ext_R7_data;
wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
mem_4096x8 mem_ext (
.R0_addr (io_imem_addr[11:0]),
.R0_en (1'h1), .R0_en (1'h1),
.R0_clk (clock), .R0_clk (clock),
.R0_data (_mem_ext_R0_data), .R0_data (io_imem_inst),
.R1_addr (io_imem_addr[11:0] + 12'h1), .R1_addr (io_dmem_addr[7:2]),
.R1_en (1'h1), .R1_en (1'h1),
.R1_clk (clock), .R1_clk (clock),
.R1_data (_mem_ext_R1_data), .R1_data (io_dmem_rdata),
.R2_addr (io_imem_addr[11:0] + 12'h2), .W0_addr (io_dmem_addr[7:2]),
.R2_en (1'h1),
.R2_clk (clock),
.R2_data (_mem_ext_R2_data),
.R3_addr (io_imem_addr[11:0] + 12'h3),
.R3_en (1'h1),
.R3_clk (clock),
.R3_data (_mem_ext_R3_data),
.R4_addr (io_dmem_addr[11:0]),
.R4_en (1'h1),
.R4_clk (clock),
.R4_data (_mem_ext_R4_data),
.R5_addr (_io_dmem_rdata_T_6),
.R5_en (1'h1),
.R5_clk (clock),
.R5_data (_mem_ext_R5_data),
.R6_addr (_io_dmem_rdata_T_3),
.R6_en (1'h1),
.R6_clk (clock),
.R6_data (_mem_ext_R6_data),
.R7_addr (_io_dmem_rdata_T),
.R7_en (1'h1),
.R7_clk (clock),
.R7_data (_mem_ext_R7_data),
.W0_addr (_io_dmem_rdata_T),
.W0_en (io_dmem_wen), .W0_en (io_dmem_wen),
.W0_clk (clock), .W0_clk (clock),
.W0_data (io_dmem_wdata[31:24]), .W0_data (io_dmem_wdata)
.W1_addr (_io_dmem_rdata_T_3),
.W1_en (io_dmem_wen),
.W1_clk (clock),
.W1_data (io_dmem_wdata[23:16]),
.W2_addr (_io_dmem_rdata_T_6),
.W2_en (io_dmem_wen),
.W2_clk (clock),
.W2_data (io_dmem_wdata[15:8]),
.W3_addr (io_dmem_addr[11:0]),
.W3_en (io_dmem_wen),
.W3_clk (clock),
.W3_data (io_dmem_wdata[7:0])
); );
assign io_imem_inst =
{_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
assign io_dmem_rdata =
{_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
endmodule endmodule
module TopOrigin( module TopOrigin(

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// format: off
// DO NOT EDIT! This file is auto-generated.
// This file enables sbt-bloop to create bloop config files.
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "2.0.6")
// format: on

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// format: off
// DO NOT EDIT! This file is auto-generated.
// This file enables sbt-bloop to create bloop config files.
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "2.0.6")
// format: on

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{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}

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[debug] not up to date. inChanged = true, force = false
[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")...
[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")

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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

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[debug] [zinc] IncrementalCompile -----------
[debug] IncrementalCompile.incrementalCompile
[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries
[debug] current source = Set()
[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())
[debug] Full compilation, no sources in previous analysis.

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[debug] Copy resource mappings: 
[debug]  

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[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files:
[debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak

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[debug] not up to date. inChanged = true, force = false
[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")...
[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")

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[debug] not up to date. inChanged = true, force = false
[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")...
[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")

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1606726032

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[debug] Other repositories:
[debug] Default repositories:

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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

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[]

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[debug] [micore-build-build] Classpath dependencies List()
[debug] [micore-build-build] Dependencies from configurations List()
[debug] Bloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json'
[success] Generated .bloop/micore-build-build.json

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[debug] Running postGenerate for micore-build-build

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[debug] [zinc] IncrementalCompile -----------
[debug] IncrementalCompile.incrementalCompile
[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries
[debug] current source = Set()
[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())
[debug] Full compilation, no sources in previous analysis.

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[debug] Copy resource mappings: 
[debug]  

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/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes

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[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files:
[debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak

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