split Hammer doc into multiple files

docs/VLSI/Advanced-Usage.rst

@@ -0,0 +1,29 @@
+.. _advanced-usage:
+
+Advanced Usage
+==============
+
+Alternative RTL Flows
+---------------------
+The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``.
+
+.. code-block:: shell
+
+    export CUSTOM_VLOG=<your verilog files>
+    export VLSI_TOP=<your top module>
+
+Manual Step Execution & Dependency Tracking
+-------------------------------------------
+It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
+
+Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par``.
+
+Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings:
+
+.. code-block:: shell
+
+   make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps'
+
+Simulation
+----------
+With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design.