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Remove references to ENABLE_YOSYS

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This commit is contained in:
abejgonzalez
2023-12-13 10:07:14 -08:00
parent f882280290
commit 088e9ea45a
6 changed files with 4 additions and 15 deletions
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2
vlsi/example-designs/sky130-openroad-rockettile.yml
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@@ -22,8 +22,6 @@ vlsi.inputs.placement_constraints:
bottom: 10
# Place SRAM memory instances
# SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
# data cache
- path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50

2
vlsi/example-designs/sky130-openroad.yml
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@@ -54,8 +54,6 @@ vlsi.inputs.placement_constraints:
bottom: 10
# Place SRAM memory instances
# SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
# data cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50

3
vlsi/tutorial.mk
View File

@@ -39,7 +39,4 @@ ifeq ($(tutorial),sky130-openroad)
example-designs/sky130-openroad-rockettile.yml, )
VLSI_OBJ_DIR ?= build-sky130-openroad
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
# Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
ENABLE_YOSYS_FLOW = 1
endif