Update section header on Verilog support in chipyard tools

2019-09-26 09:50:41 -07:00
parent 216ae3ee54
commit 28664ea8df
1 changed files with 2 additions and 2 deletions
--- a/docs/Customization/Incorporating-Verilog-Blocks.rst
+++ b/docs/Customization/Incorporating-Verilog-Blocks.rst
@@ -158,8 +158,8 @@ write.
    :start-after: DOC include start: GCD test
    :end-before: DOC include end: GCD test

-Support for Verilog in Downstream Berkeley Tools
------------------------------------------------
+Support for Verilog Within Chipyard Tool Flows
+----------------------------------------------

 There are important differences in how Verilog blackboxes are treated
 by downstream tools. Since they remain blackboxes in FIRRTL, their