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@@ -19,7 +19,6 @@ par.generate_power_straps_options:
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- met5
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blockage_spacing_met2: 4.0
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blockage_spacing_met4: 2.0
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blockage_spacing_met4: 2.0
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track_width: 3
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track_width_met5: 1
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track_spacing: 5
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@@ -74,22 +73,22 @@ vlsi.inputs.placement_constraints:
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y: 1900
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
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type: hardmacro
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x: 1000
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x: 1000
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y: 1300
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
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type: hardmacro
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x: 1000
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x: 1000
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y: 700
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
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type: hardmacro
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x: 1000
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x: 1000
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y: 100
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orientation: r0
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@@ -124,7 +123,7 @@ vlsi.inputs.placement_constraints:
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x: 2000
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y: 1900
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orientation: "r0"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
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type: hardmacro
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x: 2750
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@@ -51,22 +51,22 @@ vlsi.inputs.placement_constraints:
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y: 1900
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
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type: hardmacro
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x: 1000
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x: 1000
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y: 1300
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
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type: hardmacro
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x: 1000
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x: 1000
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y: 700
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
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type: hardmacro
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x: 1000
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x: 1000
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y: 100
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orientation: r0
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@@ -87,4 +87,4 @@ vlsi.inputs.placement_constraints:
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type: hardmacro
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x: 3450
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y: 1300
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orientation: r0
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orientation: r0
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@@ -19,4 +19,4 @@ vlsi.inputs.placement_constraints:
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left: 10
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right: 10
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top: 10
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bottom: 10
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bottom: 10
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