Run pre-commit on all files

LICENSE

@@ -27,4 +27,3 @@ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-

docs/Advanced-Concepts/CDEs.rst

@@ -107,5 +107,3 @@ In this example, note how ``up(SomeKeyY, site)`` in ``WithXEqualsYUp`` will refe
 
 
 Also note that again, ``site`` must be recursively passed through the call to ``up``.
-
-

docs/Advanced-Concepts/Debugging-RTL.rst

@@ -103,4 +103,3 @@ Firesim Debugging
 Chisel printfs, asserts, Dromajo co-simulation, and waveform generation are also available in FireSim
 FPGA-accelerated simulation. See the FireSim
 `documentation <https://docs.fires.im/en/latest/>`__ for more detail.
-

docs/Advanced-Concepts/index.rst

@@ -16,4 +16,3 @@ They expect you to know about Chisel, Parameters, configs, etc.
    CDEs
    Harness-Clocks
    Managing-Published-Scala-Dependencies
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docs/Chipyard-Basics/index.rst

@@ -19,5 +19,3 @@ Hit next to get started!
    Development-Ecosystem
    Configs-Parameters-Mixins
    Initial-Repo-Setup
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-

docs/Customization/DMA-Devices.rst

@@ -35,5 +35,3 @@ Once we've created our top-level module including the DMA widget, we can create
     :language: scala
     :start-after: DOC include start: InitZeroRocketConfig
     :end-before: DOC include end: InitZeroRocketConfig
-
-

docs/Customization/Keys-Traits-Configs.rst

@@ -75,5 +75,3 @@ We can use this config fragment when composing our configs.
 
 .. note::
    Readers who want more information on the configuration system may be interested in reading :ref:`cdes`.
-
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docs/Customization/MMIO-Peripherals.rst

@@ -138,5 +138,3 @@ Now with all of that done, we can go ahead and run our simulation.
 
     cd sims/verilator
     make CONFIG=GCDTLRocketConfig BINARY=../../tests/gcd.riscv run-binary
-
-

docs/Customization/RoCC-Accelerators.rst

@@ -67,4 +67,3 @@ For instance, if we wanted to add the previously defined accelerator and route c
       new RocketConfig)
 
 To add RoCC instructions in your program, use the RoCC C macros provided in ``tests/rocc.h``. You can find examples in the files ``tests/accum.c`` and ``charcount.c``.
-

docs/Generators/Gemmini.rst

@@ -7,4 +7,3 @@ Gemmini enables architects to make useful insights into how different components
 Check out `Gemmini's documentation <https://github.com/ucb-bar/gemmini/blob/master/README.md>`__ to learn how to generate, simulate, and profile DNN accelerators with Gemmini and Chipyard.
 
 .. image:: ../_static/images/gemmini-system.png
-

docs/Generators/SHA3.rst

@@ -79,5 +79,3 @@ this config fragment is shown here:
 
 The SHA3 example baremetal and Linux tests are located in the SHA3 repository.
 Please refer to its `README.md <https://github.com/ucb-bar/sha3/blob/master/README.md>`_ for more information on how to run/build the tests.
-
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docs/Generators/index.rst

@@ -34,4 +34,3 @@ so changes to the generators themselves will automatically be used when building
    NVDLA
    Sodor
    Mempress
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docs/TileLink-Diplomacy-Reference/Widgets.rst

@@ -465,6 +465,3 @@ if you want multi-beat reads/writes.
 AXI4RAM only supports AXI4-Lite operations, so multi-beat reads/writes and
 reads/writes smaller than full-width are not supported. Use an ``AXI4Fragmenter``
 if you want to use the full AXI4 protocol.
-
-
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docs/VLSI/Building-A-Chip.rst

@@ -50,5 +50,3 @@ Running the VLSI tool flow
 
 For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation <https://hammer-vlsi.readthedocs.io/>`__.
 For an example of how to use the VLSI in the context of Chipyard, see :ref:`VLSI/ASAP7-Tutorial:ASAP7 Tutorial`.
-
-

fpga/src/main/scala/arty/TestHarness.scala

@@ -38,4 +38,3 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
     ApplyHarnessBinders(this, d.lazySystem, d.portMap)
   }
 }
-

fpga/src/main/scala/vcu118/CustomOverlays.scala

@@ -107,4 +107,3 @@ class DDR2VCU118ShellPlacer(shell: VCU118FPGATestHarness, val shellInput: DDRShe
   extends DDRShellPlacer[VCU118FPGATestHarness] {
   def place(designInput: DDRDesignInput) = new DDR2VCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
 }
-

generators/chipyard/src/main/scala/ChipTop.scala

@@ -33,4 +33,3 @@ class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
   // anyways, they probably need to be explicitly clocked.
   lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) {  }
 }
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generators/chipyard/src/main/scala/Subsystem.scala

@@ -83,4 +83,3 @@ class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends Bas
   // This is included in the `dromajo_params.h` header file
   DromajoHelper.addArtefacts(InSubsystem)
 }
-

generators/chipyard/src/main/scala/TestHarness.scala

@@ -108,4 +108,3 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
   implicitHarnessClockBundle.reset := reset
   p(HarnessClockInstantiatorKey).instantiateHarnessDividerPLL(implicitHarnessClockBundle)
 }
-

generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala

@@ -86,4 +86,3 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
     := tileResetSetter
     := allClockGroupsNode)
 }
-

generators/chipyard/src/main/scala/config/RocketSha3Configs.scala

@@ -20,4 +20,3 @@ class Sha3RocketPrintfConfig extends Config(
   new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
-

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -75,4 +75,3 @@ class WithSerialTLBackingMemory extends Config((site, here, up) => {
 class WithExtMemIdBits(n: Int) extends Config((site, here, up) => {
     case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n)))
 })
-

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -68,4 +68,3 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
     ))
   }
 })
-

generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala

@@ -11,4 +11,3 @@ class TraceGenTop(implicit p: Parameters) extends TraceGenSystem
 class WithTracegenSystem extends Config((site, here, up) => {
   case BuildSystem => (p: Parameters) => new TraceGenTop()(p)
 })
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generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala

@@ -145,4 +145,3 @@ trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
 class WithStreamingPassthrough extends Config((site, here, up) => {
   case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8))
 })
-

generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala

@@ -23,4 +23,3 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio
     )
   )
 }
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scripts/fix-open-files.sh

@@ -11,4 +11,3 @@ fi
 
 # in any case, set the soft limit to the same value as the hard limit
 ulimit -Sn $(ulimit -Hn)
-

tests/spiflash.py

@@ -8,4 +8,3 @@ with open(outfile, 'wb') as f:
     for i in range(0,0x100000,4):
         check = 0xdeadbeef - i
         f.write(check.to_bytes(4,'little'))
-

vlsi/example-designs/sky130-commercial.yml

@@ -19,7 +19,6 @@ par.generate_power_straps_options:
       - met5
     blockage_spacing_met2: 4.0
     blockage_spacing_met4: 2.0
-    blockage_spacing_met4: 2.0
     track_width: 3
     track_width_met5: 1
     track_spacing: 5

vlsi/example-sky130.yml

@@ -54,7 +54,6 @@ par.generate_power_straps_options:
       - met5
     blockage_spacing_met2: 4.0
     blockage_spacing_met4: 2.0
-    blockage_spacing_met4: 2.0
     track_width: 3
     track_width_met5: 1
     track_spacing: 5