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support verilator | rename build variable

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This commit is contained in:
abejgonzalez
2019-04-22 23:26:13 -07:00
parent 0e5e1bac15
commit 2bd70937cb
4 changed files with 18 additions and 18 deletions
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18
variables.mk
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@@ -7,7 +7,7 @@
# descriptions:
# PROJECT = the scala package to find the MODEL/Generator in
# MODEL = the top level module of the project in Chisel (normally the harness)
# FIRRTL_MODEL = the top level module of the project in Firrtl (normally the harness)
# VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness)
# CONFIG = the configuration class to give the parameters for the project
# CFG_PROJECT = the scala package to find the CONFIG class
# SBT_PROJECT = the SBT project that you should find the Generator class in
@@ -17,14 +17,14 @@
# project specific:
# SUB_PROJECT = use the specific subproject default variables
#########################################################################################
PROJECT ?= example
MODEL ?= RocketTestHarness
FIRRTL_MODEL ?= TestHarness
CONFIG ?= DefaultRocketConfig
CFG_PROJECT ?= $(PROJECT)
SBT_PROJECT ?= $(PROJECT)
TB ?= TestDriver
TOP ?= RocketTop
PROJECT ?= example
MODEL ?= RocketTestHarness
VLOG_MODEL ?= TestHarness
CONFIG ?= DefaultRocketConfig
CFG_PROJECT ?= $(PROJECT)
SBT_PROJECT ?= $(PROJECT)
TB ?= TestDriver
TOP ?= RocketTop
# make it so that you only change 1 param to change most or all of them!
SUB_PROJECT ?= example