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Merge pull request #228 from ucb-bar/dev-asap7-demo

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ASAP7 Hammer Demo
This commit is contained in:
Abraham Gonzalez
2019-09-27 20:02:46 -07:00
committed by GitHub
parent 4853300de6 bbe457d14d
commit 3534a48b5f
23 changed files with 1242 additions and 91 deletions
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12
.gitmodules vendored
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@@ -43,9 +43,6 @@
[submodule "vlsi/hammer"]
path = vlsi/hammer
url = https://github.com/ucb-bar/hammer.git
[submodule "vlsi/hammer-cad-plugins"]
path = vlsi/hammer-cad-plugins
url = https://github.com/ucb-bar/hammer-cad-plugins.git
[submodule "tools/dsptools"]
path = tools/dsptools
url = https://github.com/ucb-bar/dsptools.git
@@ -61,3 +58,12 @@
[submodule "tools/firrtl-interpreter"]
path = tools/firrtl-interpreter
url = https://github.com/freechipsproject/firrtl-interpreter.git
[submodule "vlsi/hammer-cadence-plugins"]
path = vlsi/hammer-cadence-plugins
url = git@github.com:ucb-bar/hammer-cadence-plugins.git
[submodule "vlsi/hammer-synopsys-plugins"]
path = vlsi/hammer-synopsys-plugins
url = git@github.com:ucb-bar/hammer-synopsys-plugins.git
[submodule "vlsi/hammer-mentor-plugins"]
path = vlsi/hammer-mentor-plugins
url = git@github.com:ucb-bar/hammer-mentor-plugins.git

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@@ -0,0 +1,54 @@
.. _advanced-usage:
Advanced Usage
==============
Alternative RTL Flows
---------------------
The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile).
.. code-block:: shell
CUSTOM_VLOG=<your verilog files>
VLSI_TOP=<your top module>
``CUSTOM_VLOG`` breaks the dependency on the rest of the Chipyard infrastructure and does not start any Chisel/FIRRTL elaboration. ``VLSI_TOP`` selects the top module from your custom Verilog files.
Under the Hood
--------------
To uncover what is happening under the hood, here are the commands that are executed:
For ``make syn``:
.. code-block:: shell
./example-vlsi -e /path/to/env.yml -p /path/to/example.yml -p /path/to/inputs.yml --obj_dir /path/to/build syn
``example-vlsi`` is the entry script as explained before, ``-e`` provides the environment yml, ``-p`` points to configuration yml/jsons, ``--obj_dir`` speficies the destination directory, and ``syn`` is the action.
For ``make par``:
.. code-block:: shell
./example-vlsi -e /path/to/env.yml -p /path/to/syn-output-full.json -o /path/to/par-input.json --obj_dir /path/to/build syn-to-par
./example-vlsi -e /path/to/env.yml -p /path/to/par-input.json --obj_dir /path/to/build par
A ``syn-to-par`` action translates the synthesis output configuration into an input configuration given by ``-o``. Then, this is passed to the ``par`` action.
For more information about all the options that can be passed to the Hammer command-line driver, please see the Hammer documentation.
Manual Step Execution & Dependency Tracking
-------------------------------------------
It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par`` to run certain actions without typing out the entire Hammer command.
Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings:
.. code-block:: shell
make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps'
Simulation
----------
With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design.

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@@ -1,58 +0,0 @@
Core HAMMER
================================
`HAMMER <https://github.com/ucb-bar/hammer>`__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs.
HAMMER allows for reusability in ASIC design while still providing the designers leeway to make their own modifications.
For more information, read the `HAMMER paper <https://people.eecs.berkeley.edu/~edwardw/pubs/hammer-woset-2018.pdf>`__ and see the `GitHub repository <https://github.com/ucb-bar/hammer>`__.
Actions
-------
Actions are the top-level tasks Hammer is capable of executing (e.g. synthesis, place-and-route, etc.)
Steps
-------
Steps are the sub-components of actions that individually addressable in Hammer (e.g. placement in the place-and-route action).
Hooks
-------
Hooks are modifications to steps or actions that are programmatically defined in a Hammer configuration.
Tool Plugins
============
Hammer supports separately managed plugins for different CAD tool vendors.
The types of tools (in there hammer names) supported currently include:
* synthesis
* par
* drc
* lvs
* sram_generator
* pcb
In order to configure your tool plugin of choice, you will need to set several configuration variables.
First, you should select which specific tool you want to use by setting ``vlsi.core.<tool_type>_tool`` to the name of your tool.
For example ``vlsi.core.par_tool: "innovus"``.
You will also need to point hammer to the folder that contains your tool plugin by setting ``vlsi.core.<tool_type>_tool_path``.
This directory should include a folder with the name of the tool as specified previously, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml`` specifying the default values for any tool specific variables.
In addition you can also customize the version of the tools you use by setting ``<tool_type>.<tool_name>.version`` to a tool specific string.
Looking at the tools ``defaults.yml`` will inform you if there are other variables you would like to set for your use of this tool.
The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tools Hammer support.
This class should be a subclass of ``Hammer<tool_type>Tool``, which will be a subclass of ``HammerTool``.
Technology Plugins
==================
Hammer supports separately managed plugins for different technologies.
Configuration
=============
To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs.
You can see the current set of all available Hammer APIs `here <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/defaults.yml>`__.

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.. _hammer:
Core Hammer
================================
`Hammer <https://github.com/ucb-bar/hammer>`__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs.
Hammer allows for reusability in ASIC design while still providing the designers leeway to make their own modifications.
For more information, read the `Hammer paper <https://people.eecs.berkeley.edu/~edwardw/pubs/hammer-woset-2018.pdf>`__ and see the `GitHub repository <https://github.com/ucb-bar/hammer>`__ and associated documentation.
Hammer implements a VLSI flow using the following high-level constructs:
Actions
-------
Actions are the top-level tasks Hammer is capable of executing (e.g. synthesis, place-and-route, etc.)
Steps
-------
Steps are the sub-components of actions that individually addressable in Hammer (e.g. placement in the place-and-route action).
Hooks
-------
Hooks are modifications to steps or actions that are programmatically defined in a Hammer configuration.
Configuration (Hammer IR)
=========================
To configure a Hammer flow, supply a set ``yaml`` or ``json`` configuration files that chooses the tool and technology plugins and versions as well as any design specific configuration options. Collectively, this configuration API is referred to as Hammer IR and can be generated from higher-level abstractions.
The current set of all available Hammer APIs is codified `here <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/defaults.yml>`__.
Tool Plugins
============
Hammer supports separately managed plugins for different CAD tool vendors. You may be able to acquire access to the included Cadence, Synopsys, and Mentor plugins repositories with permission from the respective CAD tool vendor.
The types of tools (by Hammer names) supported currently include:
* synthesis
* par
* drc
* lvs
* sram_generator
* pcb
Several configuration variables are needed to configure your tool plugin of choice.
First, select which tool to use for each action by setting ``vlsi.core.<tool_type>_tool`` to the name of your tool, e.g. ``vlsi.core.par_tool: "innovus"``.
Then, point Hammer to the folder that contains your tool plugin by setting ``vlsi.core.<tool_type>_tool_path``.
This directory should include a folder with the name of the tool, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml``. Customize the version of the tool by setting ``<tool_type>.<tool_name>.version`` to a tool specific string.
The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tool.
This class should be a subclass of ``Hammer<tool_type>Tool``, which will be a subclass of ``HammerTool``. The class should implement methods for all the tool's steps.
The ``defaults.yml`` file contains tool-specific configuration variables. The defaults may be overridden as necessary.
Technology Plugins
==================
Hammer supports separately managed technology plugins to satisfy NDAs. You may be able to acquire access to certain pre-built technology plugins with permission from the technology vendor. Or, to build your own tech plugin, you need at least a ``<tech_name>.tech.json`` and ``defaults.yml``. An ``__init__.py`` is optional if there are any technology-specific methods or hooks to run.
The `ASAP7 plugin <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__ is a good starting point for setting up a technology plugin because it is an open-source example that is not suitable for taping out a chip. Refer to Hammer's documentation for the schema and detailed setup instructions.
Several configuration variables are needed to configure your technology of choice.
First, choose the technology, e.g. ``vlsi.core.technology: asap7``, then point to the location with the PDK tarball with ``technology.<tech_name>.tarball_dir`` or pre-installed directory with ``technology.<tech_name>.install_dir`` and (if applicable) the plugin repository with ``vlsi.core.technology_path``.
Technology-specific options such as supplies, MMMC corners, etc. are defined in their respective ``vlsi.inputs...`` configurations. Options for the most common use case are already defined in the technology's ``defaults.yml`` and can be overridden by the user.

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@@ -0,0 +1,140 @@
.. _tutorial:
ASAP7 Tutorial
==============
The ``vlsi`` folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS.
Project Structure
-----------------
This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders:
* Makefile
* Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands.
* build
* Hammer output directory. Can be changed with the ``OBJ_DIR`` variable.
* Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files.
* env.yml
* A template file for tool environment configuration. Fill in the install and license server paths for your environment.
* example-vlsi
* Entry point to Hammer. Contains example placeholders for hooks.
* example.v
* Verilog wrapper around the accelerator and dummy hard macro.
* example.yml
* Hammer IR for this tutorial.
* extra_libraries
* Contains collateral for the dummy hard macro.
* generated-src
* All of the elaborated Chisel and FIRRTL.
* hammer, hammer-<vendor>-plugins, hammer-<tech>-plugin
* Core, tool, tech repositories.
Prerequisites
-------------
* Python 3.4+
* numpy and gdspy packages
* Genus, Innovus, and Calibre licenses
* For ASAP7 specifically:
* Download the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball to a directory of choice but do not extract it
* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion.
Initial Setup
-------------
In the Chipyard root, run:
.. code-block:: shell
``./scripts/init-vlsi.sh asap7``
to pull the Hammer & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Pull the Hammer environment into the shell:
.. code-block:: shell
cd vlsi
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
Building the Design
-------------------
To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow:
.. code-block:: shell
make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead.
The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module.
The ``VLSI_TOP=Sha3AccelwBB`` indicates that we are only interested in physical design of the accelerator block. If this variable is not set, the entire SoC will be pushed through physical design. Note that you should not set the ``TOP`` variable because it is used during Chisel elaboration.
For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
Running the VLSI Flow
---------------------
example-vlsi
^^^^^^^^^^^^
This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter. This hook is run after ``write_design`` because the ASAP7 PDK requires post-par GDSs to be scaled down by a factor of 4.
example.yml
^^^^^^^^^^^
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
First, set ``technology.asap7.tarball_dir`` to the absolute path of where the downloaded the ASAP7 PDK tarball lives.
Synthesis
^^^^^^^^^
.. code-block:: shell
``make syn``
Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
Place-and-Route
^^^^^^^^^^^^^^^
.. code-block:: shell
``make par``
After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``.
Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes.
Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.
DRC & LVS
^^^^^^^^^
To run DRC & LVS, and view the results in Calibre:
.. code-block:: shell
make drc
./build/drc-rundir/generated-scripts/view-drc
make lvs
./build/lvs-rundir/generated-scripts/view-lvs
Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__.

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@@ -2,11 +2,13 @@ VLSI Flow
================================
The Chipyard framework aims to provide wrappers for a general VLSI flow.
In particular, we aim to support the HAMMER physical design generator flow.
In particular, we aim to support the Hammer physical design generator flow.
.. toctree::
:maxdepth: 2
:caption: VLSI Flow:
Building-A-Chip
HAMMER
Hammer
Tutorial
Advanced-Usage

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@@ -16,14 +16,18 @@ git config submodule.toolchains/esp-tools.update none
git config --global submodule.experimental-blocks.update none
# Disable updates to the FireSim submodule until explicitly requested
git config submodule.sims/firesim.update none
# Disable updates to the hammer-cad-plugins repo
git config submodule.vlsi/hammer-cad-plugins.update none
# Disable updates to the hammer tool plugins repos
git config submodule.vlsi/hammer-cadence-plugins.update none
git config submodule.vlsi/hammer-synopsys-plugins.update none
git config submodule.vlsi/hammer-mentor-plugins.update none
git submodule update --init --recursive #--jobs 8
# unignore riscv-tools,catapult-shell2 globally
git config --unset submodule.toolchains/riscv-tools.update
git config --unset submodule.toolchains/esp-tools.update
git config --global --unset submodule.experimental-blocks.update
git config --unset submodule.vlsi/hammer-cad-plugins.update
git config --unset submodule.vlsi/hammer-cadence-plugins.update
git config --unset submodule.vlsi/hammer-synopsys-plugins.update
git config --unset submodule.vlsi/hammer-mentor-plugins.update
# Renable firesim and init only the required submodules to provide
# all required scala deps, without doing a full build-setup

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scripts/init-vlsi.sh
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@@ -1,11 +1,15 @@
#!/usr/bin/env bash
# exit script if any command fails
# exit script if any command fails
set -e
set -o pipefail
# Initialize HAMMER and CAD-plugins
git submodule update --init --recursive vlsi/hammer
git submodule update --init --recursive vlsi/hammer-cad-plugins
git submodule update --init --recursive vlsi/hammer-cadence-plugins
git submodule update --init --recursive vlsi/hammer-synopsys-plugins
git submodule update --init --recursive vlsi/hammer-mentor-plugins
# Initialize HAMMER tech plugin
git submodule update --init --recursive vlsi/hammer-"$1"-plugin
if [[ $1 != *asap7* ]]; then
git submodule update --init --recursive vlsi/hammer-$1-plugin
fi

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vlsi/Makefile
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@@ -18,22 +18,30 @@ include $(base_dir)/variables.mk
# vlsi types and rules
#########################################################################################
sim_name ?= vcs # needed for GenerateSimFiles, but is unused
tech_name ?=
tech_dir ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)
tech_name ?= asap7
tech_dir ?= $(if $(filter $(tech_name), asap7), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
SMEMS_COMP ?= $(tech_dir)/sram-compiler.json
SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER)
OBJ_DIR ?= $(vlsi_dir)/build
ENV_YML ?= $(vlsi_dir)/bwrc-env.yml
INPUT_CONFS ?= example.yml $(dir $(tech_dir))/bwrc.yml
ENV_YML ?= $(vlsi_dir)/env.yml
INPUT_CONFS ?= example.yml
HAMMER_EXEC ?= ./example-vlsi
VLSI_TOP ?= $(TOP)
#########################################################################################
# general rules
#########################################################################################
ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) $(extra_v_includes)
extra_v_includes = $(build_dir)/EICG_wrapper.v
ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE)
extra_v_includes = $(build_dir)/EICG_wrapper.v $(vlsi_dir)/example.v
ifneq ($(CUSTOM_VLOG), )
VLSI_RTL = $(CUSTOM_VLOG)
VLSI_BB = /dev/null
else
VLSI_RTL = $(ALL_RTL) $(extra_v_includes)
VLSI_BB = $(sim_top_blackboxes)
endif
.PHONY: default verilog
default: all
@@ -74,14 +82,17 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
# synthesis input configuration
#########################################################################################
SYN_CONF = $(OBJ_DIR)/inputs.yml
GENERATED_CONFS = $(SYN_CONF) $(SRAM_CONF)
GENERATED_CONFS = $(SYN_CONF)
ifeq ($(CUSTOM_VLOG), )
GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF))
endif
$(SYN_CONF): $(ALL_RTL) $(extra_v_includes) $(sim_top_blackboxes)
$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
mkdir -p $(dir $@)
echo "synthesis.inputs:" > $@
echo " top_module: $(TOP)" >> $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@
for x in $(ALL_RTL) $(extra_v_includes) `cat $(sim_top_blackboxes)`; do \
for x in $(VLSI_RTL) `cat $(VLSI_BB)`; do \
echo ' - "'$$x'"' >> $@; \
done

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vlsi/README.md
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@@ -1,9 +0,0 @@
This is the starting point for a vlsi flow from this repository.
This flow will not work without the necessary CAD and technology plugins for HAMMER.
If you are a UCB-affiliate, you may be able to acquire access to the tech-plugins.
# Initial Setup Instructions (For All technologies)
Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-cad-plugins, and the hammer-tech-plugins
```scripts/init-vlsi.sh TECH_NAME```

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vlsi/env.yml Normal file
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@@ -0,0 +1,13 @@
# Base path to where Mentor tools are installed
mentor.mentor_home: ""
# Mentor license server/file
mentor.MGLS_LICENSE_FILE: ""
# Base path to where Cadence tools are installed
cadence.cadence_home: ""
# Cadence license server/file
cadence.CDS_LIC_FILE: ""
# Base path to where Synopsys tools are installed
synopsys.synopsys_home: ""
# Synopsys license server/files
synopsys.SNPSLMD_LICENSE_FILE: ""
synopsys.MGLS_LICENSE_FILE: ""

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vlsi/example-vlsi
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@@ -1,4 +1,5 @@
#!/usr/bin/env python3
import os
import hammer_vlsi
from hammer_vlsi import CLIDriver, HammerToolHookAction
@@ -8,12 +9,60 @@ from typing import Dict, Callable, Optional, List
def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
x.append('''
# TODO
# Place custom TCL here
''')
return True
def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
x.append('''
# TODO
# Place custom TCL here
''')
return True
def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
x.append('''
# TODO
# Place custom TCL here
''')
return True
def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool:
"""
Scale the final GDS by a factor of 4
"""
x.append('''
# Write script out to a temporary file and execute it
set fp [open "{script_file}" "w"]
puts -nonewline $fp "{script_text}"
close $fp
if {{ [catch {{ exec python3 {script_file} }} msg] }} {{
puts "$::errorInfo"
}}
'''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py")))
return True
class ExampleDriver(CLIDriver):
def get_extra_par_hooks(self) -> List[HammerToolHookAction]:
return [hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells)]
extra_hooks = [
# Default set of steps can be found in the CAD tool plugin's __init__.py
# make_pre_insertion_hook will execute the custom hook before the specified step
hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK)
# make_post_insertion_hook will execute the custom hook after the specified step
hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
# make_replacement_hook will replace the specified step with a custom hook
hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# make_removal_hook will remove the specified step from the flow
hammer_vlsi.HammerTool.make_removal_hook("place_bumps"),
# The target step in any of the above calls may be a default step or another one of your custom hooks
# This is an example of a technology-supplied hook (look in hammer/src/hammer-vlsi/technology/asap7/__init__.py)
hammer_vlsi.HammerTool.make_post_insertion_hook("write_design", scale_final_gds)
]
return extra_hooks
if __name__ == '__main__':
ExampleDriver().main()

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@@ -0,0 +1,65 @@
// Sha3Accel w/ a blackbox (a dummy DCO) included inside
module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2]
input clock, // @[:example.TestHarness.Sha3RocketConfig.fir@135906.4]
input reset, // @[:example.TestHarness.Sha3RocketConfig.fir@135907.4]
output io_cmd_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input io_cmd_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [6:0] io_cmd_bits_inst_funct, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [63:0] io_cmd_bits_rs1, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [63:0] io_cmd_bits_rs2, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input io_mem_req_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output io_mem_req_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output [39:0] io_mem_req_bits_addr, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output [7:0] io_mem_req_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output [4:0] io_mem_req_bits_cmd, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output [63:0] io_mem_req_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input io_mem_resp_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [7:0] io_mem_resp_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [63:0] io_mem_resp_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output io_busy, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [13:0] col_sel_b,
input [15:0] row_sel_b,
input [7:0] code_regulator,
input dither,
input sleep_b,
output dco_clock
);
Sha3Accel sha3 (
.clock(clock),
.reset(reset),
.io_cmd_ready(io_cmd_ready),
.io_cmd_valid(io_cmd_valid),
.io_cmd_bits_inst_funct(io_cmd_bits_inst_funct),
.io_cmd_bits_rs1(io_cmd_bits_rs1),
.io_cmd_bits_rs2(io_cmd_bits_rs2),
.io_mem_req_ready(io_mem_req_ready),
.io_mem_req_valid(io_mem_req_valid),
.io_mem_req_bits_addr(io_mem_req_bits_addr),
.io_mem_req_bits_tag(io_mem_req_bits_tag),
.io_mem_req_bits_cmd(io_mem_req_bits_cmd),
.io_mem_req_bits_data(io_mem_req_bits_data),
.io_mem_resp_valid(io_mem_resp_valid),
.io_mem_resp_bits_tag(io_mem_resp_bits_tag),
.io_mem_resp_bits_data(io_mem_resp_bits_data),
.io_busy(io_busy)
);
ExampleDCO dco (
.col_sel_b(col_sel_b),
.row_sel_b(row_sel_b),
.code_regulator(code_regulator),
.dither(dither),
.sleep_b(sleep_b),
.clock(dco_clock)
);
endmodule
module ExampleDCO (
input [13:0] col_sel_b,
input [15:0] row_sel_b,
input [7:0] code_regulator,
input dither,
input sleep_b,
output clock
);
endmodule

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# Technology Setup
# Technology used is ASAP7
vlsi.core.technology: asap7
# Specify dir with ASAP7 tarball
technology.asap7.tarball_dir: ""
vlsi.core.max_threads: 12
# General Hammer Inputs
# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
vlsi.inputs.power_spec_mode: "auto"
vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock", period: "1ns", uncertainty: "0.1ns"}
]
# Generate Make include to aid in flow
vlsi.core.build_system: make
# Power Straps
par.power_straps_mode: generate
par.generate_power_straps_method: by_tracks
par.blockage_spacing: 2.0
par.generate_power_straps_options:
by_tracks:
strap_layers:
- M3
- M4
- M5
- M6
- M7
- M8
- M9
track_width: 5
track_spacing: 0
track_start: 10
power_utilization: 0.05
power_utilization_M8: 1.0
power_utilization_M9: 1.0
# Placement Constraints
# For ASAP7, all numbers must be 4x larger than final GDS
vlsi.inputs.placement_constraints:
- path: "Sha3AccelwBB"
type: toplevel
x: 0
y: 0
width: 300
height: 300
margins:
left: 0
right: 0
top: 0
bottom: 1.08 #must be at least this number
- path: "Sha3AccelwBB/dco"
type: hardmacro
x: 108
y: 108
width: 128
height: 128
orientation: r0
top_layer: M9
# Pin placement constraints
vlsi.inputs.pin_mode: generated
vlsi.inputs.pin.generate_mode: semi_auto
vlsi.inputs.pin.assignments: [
{pins: "*", layers: ["M5", "M7"], side: "bottom"}
]
# Paths to extra libraries
vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]
vlsi.technology.extra_libraries:
- library:
nldm liberty file_deepsubst_meta: "local"
nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib"
lef file_deepsubst_meta: "local"
lef file: "extra_libraries/example/ExampleDCO.lef"
gds file_deepsubst_meta: "local"
gds file: "extra_libraries/example/ExampleDCO.gds"
corner:
nmos: "slow"
pmos: "slow"
temperature: "100 C"
supplies:
VDD: "0.63 V"
GND: "0 V"
- library:
nldm liberty file_deepsubst_meta: "local"
nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib"
lef file_deepsubst_meta: "local"
lef file: "extra_libraries/example/ExampleDCO.lef"
gds file_deepsubst_meta: "local"
gds file: "extra_libraries/example/ExampleDCO.gds"
corner:
nmos: "fast"
pmos: "fast"
temperature: "0 C"
supplies:
VDD: "0.77 V"
GND: "0 V"
# Because the DCO is a dummy layout, we treat it as a physical-only cell
par.inputs.physical_only_cells_mode: append
par.inputs.physical_only_cells_list:
- ExampleDCO
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: []
vlsi.core.sram_generator_tool_path_meta: "append"
# Tool options. Replace with your tool plugin of choice.
# Genus options
vlsi.core.synthesis_tool: "genus"
vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
vlsi.core.synthesis_tool_path_meta: "append"
synthesis.genus.version: "1813"
# Innovus options
vlsi.core.par_tool: "innovus"
vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
vlsi.core.par_tool_path_meta: "append"
par.innovus.version: "191"
par.innovus.design_flow_effort: "standard"
par.inputs.gds_merge: true
# Calibre options
vlsi.core.drc_tool: "calibre"
vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
vlsi.core.lvs_tool: "calibre"
vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]

BIN
vlsi/extra_libraries/example/ExampleDCO.gds Normal file
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VERSION 5.6 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
MACRO ExampleDCO
CLASS BLOCK ;
ORIGIN 0 0 ;
FOREIGN ExampleDCO 0 0 ;
SIZE 128.0 BY 128.0 ;
SYMMETRY X Y ;
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER M7 ;
RECT 32.96 124.0 33.6 128.0 ;
END
END VDD
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER M5 ;
RECT 93.12 124.0 93.76 128.0 ;
END
END VSS
PIN col_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 113.28 4.0 113.664 ;
END
END col_sel_b[13]
PIN col_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 107.648 4.0 108.032 ;
END
END col_sel_b[11]
PIN col_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 90.752 4.0 91.136 ;
END
END col_sel_b[5]
PIN col_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 110.464 4.0 110.848 ;
END
END col_sel_b[12]
PIN col_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 104.832 4.0 105.216 ;
END
END col_sel_b[10]
PIN col_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 102.016 4.0 102.4 ;
END
END col_sel_b[9]
PIN col_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 99.2 4.0 99.584 ;
END
END col_sel_b[8]
PIN col_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 96.384 4.0 96.768 ;
END
END col_sel_b[7]
PIN col_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 93.568 4.0 93.952 ;
END
END col_sel_b[6]
PIN col_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 87.936 4.0 88.32 ;
END
END col_sel_b[4]
PIN col_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 85.12 4.0 85.504 ;
END
END col_sel_b[3]
PIN col_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 82.304 4.0 82.688 ;
END
END col_sel_b[2]
PIN col_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 79.488 4.0 79.872 ;
END
END col_sel_b[1]
PIN col_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 76.672 4.0 77.056 ;
END
END col_sel_b[0]
PIN row_sel_b[14]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 71.04 4.0 71.424 ;
END
END row_sel_b[14]
PIN row_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 68.224 4.0 68.608 ;
END
END row_sel_b[13]
PIN row_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 65.408 4.0 65.792 ;
END
END row_sel_b[12]
PIN row_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 62.592 4.0 62.976 ;
END
END row_sel_b[11]
PIN row_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 59.776 4.0 60.16 ;
END
END row_sel_b[10]
PIN row_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 56.96 4.0 57.344 ;
END
END row_sel_b[9]
PIN row_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 54.144 4.0 54.528 ;
END
END row_sel_b[8]
PIN row_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 51.328 4.0 51.712 ;
END
END row_sel_b[7]
PIN row_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 48.512 4.0 48.896 ;
END
END row_sel_b[6]
PIN row_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 45.696 4.0 46.08 ;
END
END row_sel_b[5]
PIN row_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 42.88 4.0 43.264 ;
END
END row_sel_b[4]
PIN row_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 40.064 4.0 40.448 ;
END
END row_sel_b[3]
PIN row_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 37.248 4.0 37.632 ;
END
END row_sel_b[2]
PIN row_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 34.432 4.0 34.816 ;
END
END row_sel_b[1]
PIN row_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 31.616 4.0 32.0 ;
END
END row_sel_b[0]
PIN code_regulator[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 28.8 4.0 29.184 ;
END
END code_regulator[7]
PIN code_regulator[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 25.984 4.0 26.368 ;
END
END code_regulator[6]
PIN code_regulator[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 23.168 4.0 23.552 ;
END
END code_regulator[5]
PIN code_regulator[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 20.352 4.0 20.736 ;
END
END code_regulator[4]
PIN code_regulator[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 17.536 4.0 17.92 ;
END
END code_regulator[3]
PIN code_regulator[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 14.72 4.0 15.104 ;
END
END code_regulator[2]
PIN code_regulator[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 11.904 4.0 12.288 ;
END
END code_regulator[1]
PIN code_regulator[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 9.088 4.0 9.472 ;
END
END code_regulator[0]
PIN row_sel_b[15]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 73.856 4.0 74.24 ;
END
END row_sel_b[15]
PIN dither
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 6.272 4.0 6.656 ;
END
END dither
PIN sleep_b
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M5 ;
RECT 9.792 0.0 10.176 4.0 ;
END
END sleep_b
PIN clock
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 124.0 70.864 128.0 71.248 ;
END
END clock
OBS
LAYER M1 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M2 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M3 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M4 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M5 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M6 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M7 ;
RECT 4.0 4.0 124.0 124.0 ;
LAYER M8 ;
RECT 0.0 0.0 128.0 128.0 ;
LAYER M9 ;
RECT 0.0 0.0 128.0 128.0 ;
LAYER Pad ;
RECT 0.0 0.0 128.0 128.0 ;
END
END ExampleDCO
END LIBRARY

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library (ExampleDCO_PVT_0P63V_100C) {
technology (cmos);
date : "Mon Sep 2 16:01:59 2019";
comment : "Generated by dotlibber.py";
revision : 0;
delay_model : table_lookup;
simulation : true;
capacitive_load_unit (1,pf);
voltage_unit : "1V";
current_unit : "1mA";
time_unit : "1ns";
pulling_resistance_unit : "1kohm";
nom_process : 1;
nom_temperature : 100;
nom_voltage : 0.630000;
voltage_map(VDD, 0.630000);
voltage_map(VSS, 0.000000);
operating_conditions("PVT_0P63V_100C") {
process : 1;
temperature : 100;
voltage : 0.630000;
}
default_operating_conditions : PVT_0P63V_100C;
lu_table_template (constraint_template_3x3) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("0.0002, 0.0004, 0.0006");
index_2 ("0.0002, 0.0004, 0.0006");
}
lu_table_template (delay_template_8x8) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("0.0001, 0.0002, 0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008");
index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088");
}
type (bus_13_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 14 ;
bit_from : 13 ;
bit_to : 0 ;
downto : true ;
}
type (bus_15_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 16 ;
bit_from : 15 ;
bit_to : 0 ;
downto : true ;
}
type (bus_7_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 8 ;
bit_from : 7 ;
bit_to : 0 ;
downto : true ;
}
cell (ExampleDCO) {
dont_use : true;
dont_touch : true;
is_macro_cell : true;
pg_pin (VDD) {
pg_type : primary_power;
voltage_name : VDD;
}
pg_pin (VSS) {
pg_type : primary_ground;
voltage_name : VSS;
}
pin (clock) {
direction : output;
clock : true;
max_capacitance : 0.02;
related_power_pin : VDD;
related_ground_pin : VSS;
}
bus ( col_sel_b ) {
bus_type : bus_13_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( col_sel_b[13:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
bus ( row_sel_b ) {
bus_type : bus_15_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( row_sel_b[15:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
bus ( code_regulator ) {
bus_type : bus_7_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( code_regulator[7:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
pin (dither) {
direction : input;
capacitance : 0.006;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}
pin (sleep_b) {
direction : input;
capacitance : 0.006;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
}

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library (ExampleDCO_PVT_0P77V_0C) {
technology (cmos);
date : "Mon Sep 2 16:01:59 2019";
comment : "Generated by dotlibber.py";
revision : 0;
delay_model : table_lookup;
simulation : true;
capacitive_load_unit (1,pf);
voltage_unit : "1V";
current_unit : "1mA";
time_unit : "1ns";
pulling_resistance_unit : "1kohm";
nom_process : 1;
nom_temperature : 0;
nom_voltage : 0.770000;
voltage_map(VDD, 0.770000);
voltage_map(VSS, 0.000000);
operating_conditions("PVT_0P77V_0C") {
process : 1;
temperature : 0;
voltage : 0.770000;
}
default_operating_conditions : PVT_0P77V_0C;
lu_table_template (constraint_template_3x3) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("0.0001, 0.0002, 0.0003");
index_2 ("0.0001, 0.0002, 0.0003");
}
lu_table_template (delay_template_8x8) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008, 0.0009, 0.001");
index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088");
}
type (bus_13_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 14 ;
bit_from : 13 ;
bit_to : 0 ;
downto : true ;
}
type (bus_15_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 16 ;
bit_from : 15 ;
bit_to : 0 ;
downto : true ;
}
type (bus_7_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 8 ;
bit_from : 7 ;
bit_to : 0 ;
downto : true ;
}
cell (ExampleDCO) {
dont_use : true;
dont_touch : true;
is_macro_cell : true;
pg_pin (VDD) {
pg_type : primary_power;
voltage_name : VDD;
}
pg_pin (VSS) {
pg_type : primary_ground;
voltage_name : VSS;
}
pin (clock) {
direction : output;
clock : true;
max_capacitance : 0.02;
related_power_pin : VDD;
related_ground_pin : VSS;
}
bus ( col_sel_b ) {
bus_type : bus_13_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( col_sel_b[13:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
bus ( row_sel_b ) {
bus_type : bus_15_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( row_sel_b[15:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
bus ( code_regulator ) {
bus_type : bus_7_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( code_regulator[7:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
pin (dither) {
direction : input;
capacitance : 0.006;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}
pin (sleep_b) {
direction : input;
capacitance : 0.006;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
}

2
vlsi/hammer

Submodule vlsi/hammer updated: a27886fb42...1b07b9a378

1
vlsi/hammer-cad-plugins

Submodule vlsi/hammer-cad-plugins deleted from 72809f538c

1
vlsi/hammer-cadence-plugins Submodule

Submodule vlsi/hammer-cadence-plugins added at 06ce365b36

1
vlsi/hammer-mentor-plugins Submodule

Submodule vlsi/hammer-mentor-plugins added at 33ccdccf2c

1
vlsi/hammer-synopsys-plugins Submodule

Submodule vlsi/hammer-synopsys-plugins added at e0ace7345e