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Merge branch 'openroad' of https://github.com/ucb-bar/chipyard into openroad

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Nayiri K
2023-03-10 15:20:10 -08:00
parent 6dba66f56c 89a23faa00
commit 39260ac02e
5 changed files with 16 additions and 22 deletions
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1
README.md
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@@ -84,6 +84,7 @@ These additional publications cover many of the internal components used in Chip
* **FireMarshal**: N. Pemberton, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408192).
* **VLSI**
* **Hammer**: E. Wang, et al., *ISQED'20*. [PDF](https://www.isqed.org/English/Archives/2020/Technical_Sessions/113.html).
* **Hammer**: H. Liew, et al., *DAC'22*. [PDF](https://dl.acm.org/doi/abs/10.1145/3489517.3530672).
## Acknowledgements

4
docs/VLSI/ASAP7-Tutorial.rst
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@@ -126,9 +126,9 @@ To run DRC & LVS, and view the results in Calibre:
.. code-block:: shell
make drc CONFIG=TinyRocketConfig
./build/drc-rundir/generated-scripts/view-drc
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc
make lvs CONFIG=TinyRocketConfig
./build/lvs-rundir/generated-scripts/view-lvs
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs
Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/asap7>`__.
Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors.

4
docs/VLSI/Sky130-Commercial-Tutorial.rst
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@@ -161,9 +161,9 @@ To run DRC & LVS, and view the results in Calibre:
.. code-block:: shell
make drc tutorial=sky130-commercial
./build/drc-rundir/generated-scripts/view_drc
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc
make lvs tutorial=sky130-commercial
./build/lvs-rundir/generated-scripts/view_lvs
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__.

10
docs/VLSI/Sky130-OpenROAD-Tutorial.rst
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@@ -184,7 +184,7 @@ Hammer generates a convenient script to launch these sessions
.. code-block:: shell
cd ./build/par-rundir
cd ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir
./generated-scripts/open_chip
Note that the conda OpenROAD package was compiled with the GUI disabled, so in order to view the layout,
@@ -199,7 +199,7 @@ These databases can be restored using the same ``open_chip`` script for debuggin
.. code-block:: shell
cd build/par-rundir
cd build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir
./generated_scripts/open_chip -h
"
Usage: ./generated-scripts/open_chip [-t] [openroad_db_name]
@@ -215,7 +215,7 @@ These databases can be restored using the same ``open_chip`` script for debuggin
# load post-clock tree database with timing inforamtion
./generated_scripts/open_chip -t post_clock_tree
.. Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.
Various reports, including timing reports, are found in ``build/par-rundir/reports``.
See the `OpenROAD tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/par/openroad>`__ for the full list of OpenROAD tool steps and their implementations.
@@ -232,9 +232,9 @@ To run DRC & LVS in Magic & Netgen, respectively:
.. code-block:: shell
make drc tutorial=sky130-openroad
./build/drc-rundir/generated-scripts/view_drc
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc
make lvs tutorial=sky130-openroad
./build/lvs-rundir/generated-scripts/view_lvs
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
Note that in ``sky130-openroad.yml`` we have set the following YAML keys:

19
vlsi/example-asap7.yml
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@@ -37,54 +37,47 @@ vlsi.inputs.placement_constraints:
right: 0
top: 0
bottom: 0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 550
y: 25
orientation: "r0"
top_layer: "M4"
master: "SRAM1RW4096x8"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
type: hardmacro
x: 550
y: 270
orientation: "r0"
top_layer: "M4"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
type: hardmacro
x: 675
y: 25
orientation: "r0"
top_layer: "M4"
master: "SRAM1RW4096x8"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
type: hardmacro
x: 675
y: 270
orientation: "r0"
top_layer: "M4"
master: "SRAM1RW4096x8"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
type: hardmacro
x: 125
y: 150
orientation: "my"
top_layer: "M4"
master: "SRAM1RW64x21"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 0
y: 25
orientation: "my"
top_layer: "M4"
master: "SRAM1RW1024x32"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
type: hardmacro
x: 0
y: 260
orientation: "my"
top_layer: "M4"
master: "SRAM1RW1024x37"
# Pin placement constraints
vlsi.inputs.pin_mode: generated