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Cleanup | Fix BlockDevice clocking issues

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This commit is contained in:
Abraham Gonzalez
2021-03-03 19:44:55 +00:00
parent c52fce79ae
commit 3d962180be
3 changed files with 13 additions and 67 deletions
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39
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -214,40 +214,7 @@ class LBWIFRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
//// DEBUG: To check if UART works (with everything default but serdes slow and ramp up to 1GHz)
//class DebugOffchipConfig extends Config(
// new testchipip.WithSerialTLWidth(64) ++
// new testchipip.WithAsynchronousSerialSlaveCrossing ++ // SerDes <-async-> mbus. Remember SerDes master tied to fbus
// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast
// new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ // controls SerDes freq.
//
// new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // everything default to 3.2GHz
// new chipyard.config.WithPeripheryBusFrequency(3200) ++
// new chipyard.config.WithMemoryBusFrequency(3200) ++
//
// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores
// new chipyard.config.AbstractOffChipConfig) // new offchip network where AXI is in harness
//
//// have pbus=3.2GHz,/1, but others are different (fbus=/4, other=/2)
//class DebugOffchip2Config extends Config(
// new chipyard.config.WithCbusToPbusCrossingType(RationalCrossing(SlowToFast)) ++
// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++
//
// new chipyard.config.WithSystemBusFrequencyAsDefault ++
// new chipyard.config.WithSystemBusFrequency(3200 / 2) ++
//
// new chipyard.config.WithFrontBusFrequency(3200 / 4) ++
// new chipyard.config.WithPeripheryBusFrequency(3200) ++
// new chipyard.config.WithMemoryBusFrequency(3200) ++
//
// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast
// new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
//
// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores
// new chipyard.config.AbstractOffChipConfig)
// fbus=/2, other=/1
class DebugOffchip3Config extends Config(
class MulticlockAXIOverSerialConfig extends Config(
new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++
new chipyard.config.WithSystemBusFrequencyAsDefault ++
@@ -262,8 +229,10 @@ class DebugOffchip3Config extends Config(
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
new chipyard.iobinders.WithSerialTLAndPassthroughClockPunchthrough ++ // add new clock for axi domain over serdes and passthrough ios
//new testchipip.WithAXIDomainFreq(1000.0) ++ // set offchip axi domain clock freq (match FireSim DRAM)
new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
new testchipip.WithBlockDeviceLocations(
freechips.rocketchip.subsystem.PBUS,
freechips.rocketchip.subsystem.PBUS) ++ // put block device fully on PBUS to avoid clock crossings
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

39
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -204,6 +204,14 @@ class FireSimMulticlockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new FireSimRocketConfig)
class FireSimMulticlockAXIOverSerialConfig extends Config(
new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaksWithoutClocking ++ // don't inherit firesim clocking
new chipyard.MulticlockAXIOverSerialConfig
)
//**********************************************************************************
// System with 16 LargeBOOMs that can be simulated with Golden Gate optimizations
// - Requires MTModels and MCRams mixins as prefixes to the platform config
@@ -216,34 +224,3 @@ class FireSim16LargeBoomConfig extends Config(
new boom.common.WithNLargeBooms(16) ++
new chipyard.config.AbstractConfig)
// unsure if this needs to scale
//new chipyard.config.WithUART((pbusFreqMHz / 100) * BigInt(115200L)) ++
//class FireSimDebugOffchipConfig extends Config(
// new WithTracerV ++
// new WithOffchipAXINoClksSetup(3200) ++
// new chipyard.DebugOffchipConfig
//)
//class FireSimDebugOffchip2Config extends Config(
// new WithTracerV ++
// new WithOffchipAXINoClksSetup(3200) ++
// new chipyard.DebugOffchip2Config
//)
class FireSimDebugOffchip2Config extends Config(
new chipyard.config.WithUART((4000 / 100) * BigInt(115200L)) ++
new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaksWithoutClocking ++ // don't inherit firesim clocking
new chipyard.DebugOffchip3Config
)
class FireSimDebugOffchip3Config extends Config(
new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaksWithoutClocking ++ // don't inherit firesim clocking
new chipyard.DebugOffchip3Config
)

2
generators/testchipip

Submodule generators/testchipip updated: b66dd655a3...531ffb7020