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Print line entirely for Verilator

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abejgonzalez
2021-08-30 15:35:02 -07:00
parent 984a10993e
commit 42912a196b
1 changed files with 1 additions and 1 deletions
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2
common.mk
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@@ -173,7 +173,7 @@ harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp
# remove duplicate files and headers in list of simulation file inputs
########################################################################################
$(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes)
awk '{print $$1;}' $^ | sort -u | grep -v '.*\.\(svh\|h\)$$' > $@
awk '{print}' $^ | sort -u | grep -v '.*\.\(svh\|h\)$$' > $@
#########################################################################################
# helper rule to just make verilog files