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Update SiFive submodules to CHIPS fork

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This commit is contained in:
michael-etzkorn
2022-08-14 12:21:45 -05:00
parent 684a02a10f
commit 439ba9731e
1 changed files with 3 additions and 3 deletions
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6
.gitmodules vendored
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@@ -15,7 +15,7 @@
url = https://github.com/riscv-boom/riscv-boom.git
[submodule "generators/sifive-blocks"]
path = generators/sifive-blocks
url = https://github.com/sifive/sifive-blocks.git
url = https://github.com/chipsalliance/rocket-chip-blocks.git
[submodule "generators/hwacha"]
path = generators/hwacha
url = https://github.com/ucb-bar/hwacha.git
@@ -27,7 +27,7 @@
url = https://github.com/firesim/icenet.git
[submodule "generators/block-inclusivecache-sifive"]
path = generators/sifive-cache
url = https://github.com/sifive/block-inclusivecache-sifive.git
url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "toolchains/riscv-tools/riscv-gnu-toolchain"]
path = toolchains/riscv-tools/riscv-gnu-toolchain
url = https://github.com/riscv/riscv-gnu-toolchain.git
@@ -121,7 +121,7 @@
url = https://github.com/ucb-bar/riscv-sodor.git
[submodule "fpga/fpga-shells"]
path = fpga/fpga-shells
url = https://github.com/sifive/fpga-shells.git
url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
[submodule "tools/api-config-chipsalliance"]
path = tools/api-config-chipsalliance
url = https://github.com/chipsalliance/api-config-chipsalliance.git