wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge pull request #1683 from ucb-bar/uart-patch

Browse Source 
FIX: Change default UART FIFO size and combine UART Config fragments
This commit is contained in:
Jerry Zhao
2024-03-06 17:17:54 -08:00
committed by GitHub
parent 5459aa3371 34e6cb8df1
commit 44693de51d
3 changed files with 13 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
generators/chipyard/src/main/scala/config/SpikeConfigs.scala
View File

@@ -18,7 +18,8 @@ class dmiSpikeConfig extends Config(
// Avoids polling on the UART registers
class SpikeFastUARTConfig extends Config(
new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.AbstractConfig)
@@ -27,7 +28,8 @@ class SpikeFastUARTConfig extends Config(
class SpikeUltraFastConfig extends Config(
new chipyard.WithSpikeTCM ++
new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.WithBroadcastManager ++
@@ -47,7 +49,8 @@ class SpikeUltraFastDevicesConfig extends Config(
new chipyard.WithSpikeTCM ++
new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.WithBroadcastManager ++

5
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
View File

@@ -66,11 +66,12 @@ class WithNoUART extends Config((site, here, up) => {
* @param address the address of the UART device
* @param baudrate the baudrate of the UART device
*/
class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000) extends Config ((site, here, up) => {
class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000, txEntries: Int = 8, rxEntries: Int = 8) extends Config ((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq(
UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
UARTParams(address = address, nTxEntries = txEntries, nRxEntries = rxEntries, initBaudRate = baudrate))
})
// @deprecated("Use WithUART instead of WithUARTFIFOEntries", "chipyard v1.10")
class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries))
})

5
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -107,7 +107,10 @@ class WithFireSimDesignTweaks extends Config(
// Optional: reduce the width of the Serial TL interface
new testchipip.serdes.WithSerialTLWidth(4) ++
// Required*: Scale default baud rate with periphery bus frequency
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
new chipyard.config.WithUART(
baudrate=BigInt(3686400L),
txEntries=256, rxEntries=256) ++ // FireSim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
// Optional: Adds IO to attach tracerV bridges
new chipyard.config.WithTraceIO ++
// Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)