Merge remote-tracking branch 'origin/main' into serial-phits
This commit is contained in:
Jerry Zhao
2
.github/workflows/update-circt.yml
vendored
2
.github/workflows/update-circt.yml
vendored
@@ -16,7 +16,7 @@ jobs:
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- name: Update CIRCT
|
||||
uses: circt/update-circt@v1.0.0
|
||||
uses: circt/update-circt@v1
|
||||
with:
|
||||
user: 'bartender'
|
||||
email: 'firesimchipyard@gmail.com'
|
||||
|
||||
27
common.mk
27
common.mk
@@ -371,14 +371,27 @@ run-binary: check-binary $(BINARY).run
|
||||
run-binaries: check-binaries $(addsuffix .run,$(BINARIES))
|
||||
|
||||
%.run: %.check-exists $(SIM_PREREQ) | $(output_dir)
|
||||
(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
|
||||
(set -o pipefail && $(NUMA_PREFIX) $(sim) \
|
||||
$(PERMISSIVE_ON) \
|
||||
$(call get_common_sim_flags,$*) \
|
||||
$(VERBOSE_FLAGS) \
|
||||
$(PERMISSIVE_OFF) \
|
||||
$* \
|
||||
$(BINARY_ARGS) \
|
||||
</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
|
||||
|
||||
# run simulator as fast as possible (no insn disassembly)
|
||||
run-binary-fast: check-binary $(BINARY).run.fast
|
||||
run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES))
|
||||
|
||||
%.run.fast: %.check-exists $(SIM_PREREQ) | $(output_dir)
|
||||
(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(PERMISSIVE_OFF) $* </dev/null | tee $(call get_sim_out_name,$*).log)
|
||||
(set -o pipefail && $(NUMA_PREFIX) $(sim) \
|
||||
$(PERMISSIVE_ON) \
|
||||
$(call get_common_sim_flags,$*) \
|
||||
$(PERMISSIVE_OFF) \
|
||||
$* \
|
||||
$(BINARY_ARGS) \
|
||||
</dev/null | tee $(call get_sim_out_name,$*).log)
|
||||
|
||||
# run simulator with as much debug info as possible
|
||||
run-binary-debug: check-binary $(BINARY).run.debug
|
||||
@@ -386,7 +399,15 @@ run-binaries-debug: check-binaries $(addsuffix .run.debug,$(BINARIES))
|
||||
|
||||
%.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir)
|
||||
if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi
|
||||
(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$*)) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
|
||||
(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) \
|
||||
$(PERMISSIVE_ON) \
|
||||
$(call get_common_sim_flags,$*) \
|
||||
$(VERBOSE_FLAGS) \
|
||||
$(call get_waveform_flag,$(call get_sim_out_name,$*)) \
|
||||
$(PERMISSIVE_OFF) \
|
||||
$* \
|
||||
$(BINARY_ARGS) \
|
||||
</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
|
||||
|
||||
run-fast: run-asm-tests-fast run-bmark-tests-fast
|
||||
|
||||
|
||||
@@ -15,8 +15,8 @@ Running on AWS EC2 with FireSim
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
If you plan on using Chipyard alongside FireSim on AWS EC2 instances, you should refer to the :fsim_doc:`FireSim documentation <>`.
|
||||
Specifically, you should follow the :fsim_doc:`Initial Setup/Installation <Initial-Setup/index.html>`
|
||||
section of the docs up until :fsim_doc:`Setting up the FireSim Repo <Initial-Setup/Setting-up-your-Manager-Instance.html#setting-up-the-firesim-repo>`.
|
||||
Specifically, you should follow the :fsim_doc:`Initial Setup/Installation <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/index.html>`
|
||||
section of the docs up until :fsim_doc:`Setting up the FireSim Repo <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Setting-up-your-Manager-Instance.html#setting-up-the-firesim-repo>`.
|
||||
At that point, instead of cloning FireSim you can clone Chipyard by following :ref:`Chipyard-Basics/Initial-Repo-Setup:Setting up the Chipyard Repo`.
|
||||
|
||||
Default Requirements Installation
|
||||
|
||||
@@ -26,12 +26,14 @@ Finally, source the following environment at the root of the FireSim directory:
|
||||
|
||||
cd sims/firesim
|
||||
# (Recommended) The default manager environment (includes env.sh)
|
||||
source sourceme-manager.sh
|
||||
source sourceme-manager.sh`
|
||||
# Completing setup using the manager
|
||||
firesim managerinit --platform f1
|
||||
|
||||
.. Note:: Every time you want to use FireSim with a fresh shell, you must source ``sourceme-manager.sh``
|
||||
|
||||
At this point you're ready to use FireSim with Chipyard. If you're not already
|
||||
familiar with FireSim, please return to the :fsim_doc:`FireSim Docs <Initial-Setup/Setting-up-your-Manager-Instance.html#completing-setup-using-the-manager>`,
|
||||
familiar with FireSim, please return to the :fsim_doc:`FireSim Docs <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Setting-up-your-Manager-Instance.html#completing-setup-using-the-manager>`,
|
||||
and proceed with the rest of the tutorial.
|
||||
|
||||
Running your Design in FireSim
|
||||
@@ -47,7 +49,7 @@ A FireSim simulation requires 3 additional config fragments:
|
||||
|
||||
|
||||
The simplest method to add this config fragments to your custom Chipyard config is through FireSim's build recipe scheme.
|
||||
After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/deploy/config_build_recipes.ini``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
|
||||
After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/config_build_recipes.yaml``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
|
||||
|
||||
An alternative method to prepending the FireSim config fragments in the FireSim build recipe is to create a new "permanent" FireChip custom configuration, which includes the FireSim config fragments.
|
||||
We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``.
|
||||
@@ -59,3 +61,5 @@ We are using the same target (top) RTL, and only need to specify a new set of co
|
||||
:end-before: DOC include end: firesimconfig
|
||||
|
||||
While this option seems to require the maintenance of additional configuration code, it has the benefit of allowing for the inclusion of more complex config fragments which also accept custom arguments (for example, ``WithDefaultMemModel`` can take an optional argument``)
|
||||
|
||||
For more information on how to build your own hardware design on FireSim, please refer to :fsim_doc:`FireSim Docs <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Building-a-FireSim-AFI.html#building-your-own-hardware-designs-firesim-amazon-fpga-images>`.
|
||||
|
||||
@@ -54,11 +54,11 @@ class WithVCU118Tweaks extends Config(
|
||||
new WithUART ++
|
||||
new WithSPISDCard ++
|
||||
new WithDDRMem ++
|
||||
new WithJTAG ++
|
||||
// other configuration
|
||||
new WithDefaultPeripherals ++
|
||||
new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
|
||||
new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
|
||||
new chipyard.config.WithNoDebug ++ // remove debug module
|
||||
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
|
||||
new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
|
||||
)
|
||||
|
||||
@@ -36,3 +36,17 @@ class WithDDRMem extends HarnessBinder({
|
||||
ddrClientBundle <> port.io
|
||||
}
|
||||
})
|
||||
|
||||
class WithJTAG extends HarnessBinder({
|
||||
case (th: VCU118FPGATestHarnessImp, port: JTAGPort, chipId: Int) => {
|
||||
val jtag_io = th.vcu118Outer.jtagPlacedOverlay.overlayOutput.jtag.getWrappedValue
|
||||
port.io.TCK := jtag_io.TCK
|
||||
port.io.TMS := jtag_io.TMS
|
||||
port.io.TDI := jtag_io.TDI
|
||||
jtag_io.TDO.data := port.io.TDO
|
||||
jtag_io.TDO.driven := true.B
|
||||
// ignore srst_n
|
||||
jtag_io.srst_n := DontCare
|
||||
|
||||
}
|
||||
})
|
||||
|
||||
@@ -85,6 +85,9 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
|
||||
)))))
|
||||
ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient
|
||||
|
||||
/*** JTAG ***/
|
||||
val jtagPlacedOverlay = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput())
|
||||
|
||||
// module implementation
|
||||
override lazy val module = new VCU118FPGATestHarnessImp(this)
|
||||
}
|
||||
|
||||
@@ -22,6 +22,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
|
||||
with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
|
||||
with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs
|
||||
with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
|
||||
with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device
|
||||
with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
|
||||
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
|
||||
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
|
||||
|
||||
@@ -11,24 +11,31 @@ import org.chipsalliance.cde.config.{Config}
|
||||
// --------------
|
||||
|
||||
class AbstractConfig extends Config(
|
||||
// ================================================
|
||||
// Set up TestHarness
|
||||
// ================================================
|
||||
// The HarnessBinders control generation of hardware in the TestHarness
|
||||
new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
|
||||
new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
|
||||
new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM
|
||||
new chipyard.harness.WithSimJTAGDebug ++ // add SimJTAG if JTAG for debug exposed
|
||||
new chipyard.harness.WithSimDMI ++ // add SimJTAG if DMI exposed
|
||||
new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present
|
||||
new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled
|
||||
new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled
|
||||
new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present
|
||||
new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present
|
||||
new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present
|
||||
new chipyard.harness.WithDriveChipIdPin ++ // drive chip id pin from harness binder, if chip id pin is present
|
||||
new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port
|
||||
new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator
|
||||
new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness
|
||||
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz
|
||||
new chipyard.harness.WithUARTAdapter ++ /** add UART adapter to display UART on stdout, if uart is present */
|
||||
new chipyard.harness.WithBlackBoxSimMem ++ /** add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled */
|
||||
new chipyard.harness.WithSimTSIOverSerialTL ++ /** add external serial-adapter and RAM */
|
||||
new chipyard.harness.WithSimJTAGDebug ++ /** add SimJTAG if JTAG for debug exposed */
|
||||
new chipyard.harness.WithSimDMI ++ /** add SimJTAG if DMI exposed */
|
||||
new chipyard.harness.WithGPIOTiedOff ++ /** tie-off chiptop GPIOs, if GPIOs are present */
|
||||
new chipyard.harness.WithSimSPIFlashModel ++ /** add simulated SPI flash memory, if SPI is enabled */
|
||||
new chipyard.harness.WithSimAXIMMIO ++ /** add SimAXIMem for axi4 mmio port, if enabled */
|
||||
new chipyard.harness.WithTieOffInterrupts ++ /** tie-off interrupt ports, if present */
|
||||
new chipyard.harness.WithTieOffL2FBusAXI ++ /** tie-off external AXI4 master, if present */
|
||||
new chipyard.harness.WithCustomBootPinPlusArg ++ /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */
|
||||
new chipyard.harness.WithDriveChipIdPin ++ /** drive chip id pin from harness binder, if chip id pin is present */
|
||||
new chipyard.harness.WithSimUARTToUARTTSI ++ /** connect a SimUART to the UART-TSI port */
|
||||
new chipyard.harness.WithClockFromHarness ++ /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */
|
||||
new chipyard.harness.WithResetFromHarness ++ /** reset controlled by harness */
|
||||
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */
|
||||
|
||||
|
||||
// ================================================
|
||||
// Set up I/O cells + punch I/Os in ChipTop
|
||||
// ================================================
|
||||
// The IOBinders instantiate ChipTop IOs to match desired digital IOs
|
||||
// IOCells are generated for "Chip-like" IOs
|
||||
new chipyard.iobinders.WithSerialTLIOCells ++
|
||||
@@ -53,42 +60,98 @@ class AbstractConfig extends Config(
|
||||
new chipyard.iobinders.WithUARTTSIPunchthrough ++
|
||||
new chipyard.iobinders.WithNMITiedOff ++
|
||||
|
||||
new chipyard.clocking.WithClockTapIOCells ++ // Default generate a clock tapio
|
||||
new chipyard.clocking.WithPassthroughClockGenerator ++ // Default punch out IOs to the Harness
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", // Default merge all the bus clocks
|
||||
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"), Seq("tile"))) ++
|
||||
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
|
||||
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
|
||||
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
|
||||
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
|
||||
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus
|
||||
new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus
|
||||
new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus
|
||||
|
||||
new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
|
||||
new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
|
||||
new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface
|
||||
// ================================================
|
||||
// Set up External Memory and IO Devices
|
||||
// ================================================
|
||||
// External memory section
|
||||
new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */
|
||||
testchipip.serdes.SerialTLParams(
|
||||
client = Some(testchipip.serdes.SerialTLClientParams()), // serial-tilelink interface will master the FBUS, and support 4 idBits
|
||||
client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
|
||||
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) // serial-tilelink interface with 32 lanes
|
||||
)
|
||||
)) ++
|
||||
new testchipip.soc.WithMbusScratchpad(base = 0x08000000, // add 64 KiB on-chip scratchpad
|
||||
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 AXI-4 memory channels */
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */
|
||||
|
||||
// MMIO device section
|
||||
new chipyard.config.WithUART ++ /** add a UART */
|
||||
|
||||
|
||||
// ================================================
|
||||
// Set up Debug/Bringup/Testing Features
|
||||
// ================================================
|
||||
// JTAG
|
||||
new freechips.rocketchip.subsystem.WithDebugSBA ++ /** enable the SBA (system-bus-access) feature of the debug module */
|
||||
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data word capacity */
|
||||
new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */
|
||||
|
||||
// Boot Select Pins
|
||||
new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */
|
||||
new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */
|
||||
|
||||
|
||||
// ================================================
|
||||
// Set up Interrupts
|
||||
// ================================================
|
||||
// CLINT and PLIC related settings goes here
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */
|
||||
|
||||
|
||||
// ================================================
|
||||
// Set up Tiles
|
||||
// ================================================
|
||||
// tile-local settings goes here
|
||||
|
||||
|
||||
// ================================================
|
||||
// Set up Memory system
|
||||
// ================================================
|
||||
// On-chip memory section
|
||||
new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS (embedded in BootROM) */
|
||||
new chipyard.config.WithBootROM ++ /** use default bootrom */
|
||||
new testchipip.soc.WithMbusScratchpad(base = 0x08000000, /** add 64 KiB on-chip scratchpad */
|
||||
size = 64 * 1024) ++
|
||||
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity
|
||||
new chipyard.config.WithBootROM ++ // use default bootrom
|
||||
new chipyard.config.WithUART ++ // add a UART
|
||||
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
|
||||
new chipyard.config.WithNoSubsystemClockIO ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
|
||||
new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set
|
||||
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels
|
||||
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
|
||||
new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
|
||||
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
|
||||
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
|
||||
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
|
||||
new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2
|
||||
new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS
|
||||
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
|
||||
|
||||
// Coherency settings
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive LLC cache as root of coherence */
|
||||
|
||||
// Bus/interconnect settings
|
||||
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
|
||||
|
||||
|
||||
// ================================================
|
||||
// Set up power, reset and clocking
|
||||
// ================================================
|
||||
|
||||
// ChipTop clock IO/PLL/Divider/Mux settings
|
||||
new chipyard.clocking.WithClockTapIOCells ++ /** Default generate a clock tapio */
|
||||
new chipyard.clocking.WithPassthroughClockGenerator ++
|
||||
|
||||
// DigitalTop-internal clocking settings
|
||||
new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */
|
||||
new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */
|
||||
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", /** create a "uncore" clock group tieing all the bus clocks together */
|
||||
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"),
|
||||
Seq("tile"))) ++
|
||||
|
||||
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */
|
||||
new chipyard.config.WithMemoryBusFrequency(500.0) ++ /** Default 500 MHz mbus */
|
||||
new chipyard.config.WithControlBusFrequency(500.0) ++ /** Default 500 MHz cbus */
|
||||
new chipyard.config.WithSystemBusFrequency(500.0) ++ /** Default 500 MHz sbus */
|
||||
new chipyard.config.WithFrontBusFrequency(500.0) ++ /** Default 500 MHz fbus */
|
||||
new chipyard.config.WithOffchipBusFrequency(500.0) ++ /** Default 500 MHz obus */
|
||||
new chipyard.config.WithInheritBusFrequencyAssignments ++ /** Unspecified clocks within a bus will receive the bus frequency if set */
|
||||
new chipyard.config.WithNoSubsystemClockIO ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */
|
||||
|
||||
// reset
|
||||
|
||||
// power
|
||||
|
||||
|
||||
// ==================================
|
||||
// Base Settings
|
||||
// ==================================
|
||||
new freechips.rocketchip.system.BaseConfig /** "base" rocketchip system */
|
||||
)
|
||||
|
||||
@@ -75,6 +75,7 @@ class ManyPeripheralsRocketConfig extends Config(
|
||||
new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
|
||||
new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
|
||||
new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
|
||||
new chipyard.config.WithPeripheryTimer ++ // add the pwm timer device
|
||||
new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
|
||||
new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
|
||||
new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
|
||||
|
||||
@@ -16,6 +16,7 @@ import sifive.blocks.devices.gpio._
|
||||
import sifive.blocks.devices.uart._
|
||||
import sifive.blocks.devices.spi._
|
||||
import sifive.blocks.devices.i2c._
|
||||
import sifive.blocks.devices.timer._
|
||||
|
||||
import testchipip._
|
||||
|
||||
@@ -168,3 +169,7 @@ class WithNoBusErrorDevices extends Config((site, here, up) => {
|
||||
case MemoryBusKey => up(MemoryBusKey).copy(errorDevice = None)
|
||||
case FrontBusKey => up(FrontBusKey).copy(errorDevice = None)
|
||||
})
|
||||
|
||||
class WithPeripheryTimer(timerParams: TimerParams = TimerParams(0x4000)) extends Config((site, here, up) => {
|
||||
case PeripheryTimerKey => Seq(timerParams)
|
||||
})
|
||||
|
||||
@@ -174,6 +174,7 @@ class WithGPIOCells extends OverrideIOBinder({
|
||||
iocell.io.oe := pin.o.oe
|
||||
iocell.io.ie := pin.o.ie
|
||||
pin.i.ival := iocell.io.i
|
||||
pin.i.po.foreach(_ := DontCare)
|
||||
iocell.io.pad <> g
|
||||
(GPIOPort(() => g, i, j), iocell)
|
||||
}).unzip
|
||||
|
||||
@@ -360,3 +360,10 @@ class FireSimLeanGemminiRocketMMIOOnlyConfig extends Config(
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.LeanGemminiRocketConfig)
|
||||
|
||||
class FireSimLargeBoomCospikeConfig extends Config(
|
||||
new firesim.firesim.WithCospikeBridge ++
|
||||
new WithDefaultFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks++
|
||||
new chipyard.LargeBoomConfig)
|
||||
|
||||
Submodule generators/rocket-chip-blocks updated: 3dddfe9f5b...f9263535be
@@ -110,7 +110,7 @@ def generate_copy(c, sfx):
|
||||
new_file = os.path.join(args.gcpath, new_file)
|
||||
|
||||
shutil.copy(cur_file, new_file)
|
||||
bash(f"{SED} -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}")
|
||||
bash(rf"{SED} -i 's/module\( \+\){cur_name}/module\1{new_name}/' {new_file}")
|
||||
return new_file
|
||||
|
||||
def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
|
||||
@@ -137,7 +137,7 @@ def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
|
||||
new_file = generate_copy(cur_file, MODEL_SFX)
|
||||
if parent is not None and ((parent, mod) not in updated_submodule):
|
||||
parent_file = os.path.join(args.gcpath, verilog_module_filename[parent])
|
||||
bash(f"{SED} -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}")
|
||||
bash(rf"{SED} -i 's/\( \*\){mod}\( \+\)/\1{mod}_{MODEL_SFX}\2/' {parent_file}")
|
||||
updated_submodule.add((parent, mod))
|
||||
|
||||
# add the uniquified module to the verilog_modul_filename dict
|
||||
|
||||
@@ -27,6 +27,7 @@ HELP_SIMULATION_VARIABLES = \
|
||||
" BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \
|
||||
" BINARIES = list of riscv elf binary that the simulator will run when using the run-binaries* targets" \
|
||||
" BINARIES_DIR = directory of riscv elf binaries that the simulator will run when using the run-binaries* targets" \
|
||||
" BINARY_ARGS = arguments to pass to each binary in run-binary targets (primarily meant for pk arguments)" \
|
||||
" LOADMEM = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \
|
||||
" LOADARCH = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \
|
||||
" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \
|
||||
@@ -275,6 +276,7 @@ PERMISSIVE_ON=+permissive
|
||||
PERMISSIVE_OFF=+permissive-off
|
||||
BINARY ?=
|
||||
BINARIES ?=
|
||||
BINARY_ARGS ?=
|
||||
override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(TIMEOUT_CYCLES)
|
||||
VERBOSE_FLAGS ?= +verbose
|
||||
# get_out_name is a function, 1st argument is the binary
|
||||
|
||||
Reference in New Issue
Block a user