[docs][ci skip] Address comments

docs/Advanced-Concepts/Debugging-RTL.rst

@@ -7,13 +7,16 @@ IP, or by modifying existing Chisel generators. Such changes might introduce
 bugs. This section aims to run through a typical debugging flow
 using Chipyard. We assume the user has a custom SoC configuration,
 and is trying to verify functionality by running some software test.
+We also assume the software has already been verified on a functional
+simulator, such as Spike or QEMU. This section will focus on debugging
+hardware.
 
 Waveforms
 ---------------------------
 
-The default SW simulators do not dump waveforms during execution. To build
-simulators with wave dump capabilities use must use the ``debug`` make target.
-For example:
+The default software RTL simulators do not dump waveforms during execution.
+To build simulators with wave dump capabilities use must use the ``debug``
+make target. For example:
 
 .. code-block:: shell
 
@@ -81,5 +84,6 @@ directory.
 Firesim Debugging
 ---------------------------
 Chisel printfs, asserts, and waveform generation are also available in FireSim
-FPGA-accelerated simulation. See the FireSim docs for more detail.
+FPGA-accelerated simulation. See the FireSim
+`documentation <https://docs.fires.im/en/latest/>`__ for more detail.
 

docs/Advanced-Concepts/index.rst

@@ -10,4 +10,5 @@ They expect you to know about Chisel, Parameters, Configs, etc.
 
    Top-Testharness
    Chip-Communication
+   Debugging-RTL
    Resources

docs/Chipyard-Basics/index.rst

@@ -18,6 +18,5 @@ Hit next to get started!
    Chipyard-Components
    Configs-Parameters-Mixins
    Initial-Repo-Setup
-   Debugging-RTL