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Fix ChipLikeQuadRocketConfig crossing

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There needs to be a crossing between sbus/fbus when they are on separate clock domains
This commit is contained in:
Jerry Zhao
2023-04-11 17:44:24 -07:00
committed by GitHub
parent 4f8ccc738c
commit 4adb8d91c1
1 changed files with 1 additions and 0 deletions
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generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -35,6 +35,7 @@ class ChipLikeQuadRocketConfig extends Config(
new chipyard.clocking.WithClockGroupsCombinedByName("fbus", "fbus", "pbus") ++
// Set up the crossings
new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between SBUS and FBUS
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS