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Move clock tap to its own async domain

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This commit is contained in:
Jerry Zhao
2023-12-18 09:23:42 -08:00
parent 2f1012294d
commit 4b9e9dacbc
4 changed files with 7 additions and 12 deletions
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13
generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
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@@ -10,18 +10,13 @@ import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.prci._
case class ClockTapParams(
busWhere: TLBusWrapperLocation = SBUS, // by default, tap the sbus clock as a debug clock
divider: Int = 16, // a fixed clock division ratio for the clock tap
)
case object ClockTapKey extends Field[Option[ClockTapParams]](Some(ClockTapParams()))
case object ClockTapKey extends Field[Boolean](true)
trait CanHaveClockTap { this: BaseSubsystem =>
val clockTapNode = p(ClockTapKey).map { tapParams =>
require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven")
val clockTapNode = Option.when(p(ClockTapKey)) {
val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
val clockTapDivider = LazyModule(new ClockDivider(tapParams.divider))
clockTap := clockTapDivider.node := locateTLBusWrapper(tapParams.busWhere).fixedClockNode
clockTap := ClockGroup() := asyncClockGroupsNode
clockTap
}
val clockTapIO = clockTapNode.map { node => InModuleBody {

2
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -54,7 +54,7 @@ class AbstractConfig extends Config(
new chipyard.clocking.WithClockTapIOCells ++ // Default generate a clock tapio
new chipyard.clocking.WithPassthroughClockGenerator ++ // Default punch out IOs to the Harness
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", // Default merge all the bus clocks
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"), Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus

2
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -60,7 +60,7 @@ class MulticlockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
// Frequency specifications
new chipyard.config.WithTileFrequency(1000.0) ++ // Matches the maximum frequency of U540
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit"), Nil),
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit", "clock_tap"), Nil),
("periphery", Seq("pbus", "fbus"), Nil)) ++
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Matches the maximum frequency of U540
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Matches the maximum frequency of U540

2
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
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@@ -130,5 +130,5 @@ class WithNoResetSynchronizers extends Config((site, here, up) => {
// Remove any ClockTap ports in this system
class WithNoClockTap extends Config((site, here, up) => {
case ClockTapKey => None
case ClockTapKey => false
})