Merge remote-tracking branch 'origin/main' into tcip-bump

.github/scripts/check-commit.sh

@@ -45,7 +45,7 @@ search () {
     done
 }
 
-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle")
+submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat")
 dir="generators"
 branches=("master" "main" "dev")
 search
@@ -81,14 +81,20 @@ dir="toolchains"
 branches=("master")
 search
 
+submodules=("firesim")
+dir="sims"
+branches=("main")
+search
+
+
 submodules=("coremark" "firemarshal" "nvdla-workload" "spec2017")
 dir="software"
 branches=("master" "dev")
 search
 
-submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture")
+submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde")
 dir="tools"
-branches=("master" "dev")
+branches=("master" "dev" "main")
 search
 
 submodules=("fpga-shells")

docs/Customization/Boot-Process.rst

@@ -12,7 +12,7 @@ Device Tree Binary (dtb) which details the components of the system.
 The assembly for the BootROM code is located in
 `generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.S <https://github.com/ucb-bar/testchipip/blob/master/src/main/resources/testchipip/bootrom/bootrom.S>`_.
 The BootROM address space starts at ``0x10000`` (determined by the ``BootROMParams`` key in the configuration) and execution starts at address
-``0x10040`` (given by the linker script and reset vector in the ``BootROMParams``), which is marked by the ``_hang`` label in the BootROM assembly.
+``0x10000`` (given by the linker script and reset vector in the ``BootROMParams``), which is marked by the ``_hang`` label in the BootROM assembly.
 
 The Chisel generator encodes the assembled instructions into the BootROM
 hardware at elaboration time, so if you want to change the BootROM code, you

docs/Prototyping/Arty.rst

@@ -34,7 +34,7 @@ Probe an address on the target system:
 
 .. code-block:: shell
 
-		./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10040 none
+		./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10000 none
 
 Write some address before running a program:
 

docs/Prototyping/NexysVideo.rst

@@ -34,7 +34,7 @@ Probe an address on the target system:
 
 .. code-block:: shell
 
-		./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10040 none
+		./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10000 none
 
 Write some address before running a program:
 

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -29,7 +29,7 @@ import chipyard.{ExtTLMem}
   * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset
   * @param contentFileName the path to the BootROM image
   */
-class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => {
+class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10000) extends Config((site, here, up) => {
   case BootROMLocated(x) => up(BootROMLocated(x), site)
       .map(_.copy(
         address = address,

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -66,6 +66,15 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
   }
 })
 
+class WithRocketCacheRowBits(rowBits: Int = 64) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      dcache = tp.tileParams.dcache.map(_.copy(rowBits = rowBits)),
+      icache = tp.tileParams.icache.map(_.copy(rowBits = rowBits))
+    ))
+  }
+})
+
 class WithRocketICacheScratchpad extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(

vlsi/tutorial.mk

@@ -12,6 +12,7 @@ ifeq ($(tutorial),asap7)
     TECH_CONF         ?= example-asap7.yml
     DESIGN_CONFS      ?=
     VLSI_OBJ_DIR      ?= build-asap7-commercial
+    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
 endif
 
 ifeq ($(tutorial),sky130-commercial)
@@ -23,6 +24,7 @@ ifeq ($(tutorial),sky130-commercial)
                         $(if $(filter $(VLSI_TOP),Rocket), \
                             example-designs/sky130-rocket.yml, )
     VLSI_OBJ_DIR      ?= build-sky130-commercial
+    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
 endif
 
 ifeq ($(tutorial),sky130-openroad)
@@ -36,8 +38,8 @@ ifeq ($(tutorial),sky130-openroad)
                         $(if $(filter $(VLSI_TOP),RocketTile), \
                             example-designs/sky130-openroad-rockettile.yml, )
     VLSI_OBJ_DIR      ?= build-sky130-openroad
+    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
     # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
     ENABLE_YOSYS_FLOW  = 1
 endif
 
-INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)