Fix more bugs with arty100t

fpga/Makefile

@@ -77,7 +77,7 @@ ifeq ($(SUB_PROJECT),arty100t)
 	MODEL             ?= Arty100THarness
 	VLOG_MODEL        ?= Arty100THarness
 	MODEL_PACKAGE     ?= chipyard.fpga.arty100t
-	CONFIG            ?= RocketArtyConfig
+	CONFIG            ?= RocketArty100TConfig
 	CONFIG_PACKAGE    ?= chipyard.fpga.arty100t
 	GENERATOR_PACKAGE ?= chipyard
 	TB                ?= none # unused

fpga/src/main/scala/arty100t/Configs.scala

@@ -26,15 +26,33 @@ class WithArty100TTweaks extends Config(
   new WithArty100TDDRTL ++
   new WithNoDesignKey ++
   new chipyard.config.WithNoDebug ++ // no jtag
-  new chipyard.config.WithNoUART ++
+  new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
   new chipyard.config.WithTLBackingMemory ++
-  new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) // 256mb on ARTY
+  new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
+  new freechips.rocketchip.subsystem.WithoutTLMonitors
 )
 
-class RocketArtyConfig extends Config(
+class RocketArty100TConfig extends Config(
   new WithArty100TTweaks ++
-  new chipyard.config.WithMemoryBusFrequency(10.0) ++  // 2x the U540 freq (appropriate for a 128b Mbus)
+  new chipyard.config.WithMemoryBusFrequency(10.0) ++
   new chipyard.config.WithPeripheryBusFrequency(10.0) ++  // Match the sbus and pbus frequency
   new chipyard.config.WithBroadcastManager ++ // no l2
   new chipyard.RocketConfig
 )
+
+class NoCoresArty100TConfig extends Config(
+  new WithArty100TTweaks ++
+  new chipyard.config.WithMemoryBusFrequency(10.0) ++
+  new chipyard.config.WithPeripheryBusFrequency(10.0) ++  // Match the sbus and pbus frequency
+  new chipyard.config.WithBroadcastManager ++ // no l2
+  new chipyard.NoCoresConfig
+)
+
+class InitZeroNoCoresArty100TConfig extends Config(
+  new WithArty100TTweaks ++
+  new chipyard.example.WithInitZero(0x80000000L, 0x1000L) ++
+  new chipyard.config.WithMemoryBusFrequency(10.0) ++
+  new chipyard.config.WithPeripheryBusFrequency(10.0) ++  // Match the sbus and pbus frequency
+  new chipyard.config.WithBroadcastManager ++ // no l2
+  new chipyard.NoCoresConfig
+)

fpga/src/main/scala/arty100t/Harness.scala

@@ -1,7 +1,7 @@
 package chipyard.fpga.arty100t
 
 import chisel3._
-
+import chisel3.util._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode}
@@ -24,19 +24,20 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
   val chiptop = LazyModule(p(BuildTop)(p))
 
   val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
-  val harnessSysPLL = dp(PLLFactoryKey)()
+  val harnessSysPLL = dp(PLLFactoryKey)
+  val harnessSysPLLNode = harnessSysPLL()
   println(s"Arty100T FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
   val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
   val dutWrangler = LazyModule(new ResetWrangler)
   val dutGroup = ClockGroup()
-  dutClock := dutWrangler.node := dutGroup := harnessSysPLL
+  dutClock := dutWrangler.node := dutGroup := harnessSysPLLNode
 
-  harnessSysPLL := clockOverlay.overlayOutput.node
+  harnessSysPLLNode := clockOverlay.overlayOutput.node
 
   val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
   val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
 
-  val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL))
+  val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
   val ddrInParams = chiptop match { case td: ChipTop =>
     td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
       lsys.memTLNode.edges.in(0)
@@ -45,11 +46,39 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
   val ddrClient = TLClientNode(Seq(ddrInParams.master))
   ddrOverlay.overlayOutput.ddr := ddrClient
 
+  val ledOverlays = dp(LEDOverlayKey).map(_.place(LEDDesignInput()))
+  val all_leds = ledOverlays.map(_.overlayOutput.led)
+  val status_leds = all_leds.take(3)
+  val other_leds = all_leds.drop(3)
+
   def buildtopClock = dutClock.in.head._1.clock
   def buildtopReset = dutClock.in.head._1.reset
   def success = { require(false, "Unused"); false.B }
 
   InModuleBody {
+    clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin
+
+    val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock
+
+    // Blink the status LEDs for sanity
+    withClock(clk_100mhz) {
+      val period = (BigInt(100) << 20) / status_leds.size
+      val counter = RegInit(0.U(log2Ceil(period).W))
+      val on = RegInit(0.U(log2Ceil(status_leds.size).W))
+      status_leds.zipWithIndex.map { case (o,s) => o := on === s.U }
+      counter := Mux(counter === (period-1).U, 0.U, counter + 1.U)
+      when (counter === 0.U) {
+        on := Mux(on === (status_leds.size-1).U, 0.U, on + 1.U)
+      }
+    }
+
+    other_leds(0) := resetPin
+
+    harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)
+
+    ddrOverlay.mig.module.clock := buildtopClock
+    ddrOverlay.mig.module.reset := buildtopReset
+
     chiptop match { case d: HasIOBinders =>
       ApplyHarnessBinders(this, d.lazySystem, d.portMap)
     }

fpga/src/main/scala/arty100t/HarnessBinders.scala

@@ -24,13 +24,24 @@ class WithArty100TUARTTSI extends OverrideHarnessBinder({
   (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
     ports.map({ port =>
+      val ath = th.asInstanceOf[Arty100THarness]
       val freq = p(PeripheryBusKey).dtsFrequency.get
       val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
       withClockAndReset(th.buildtopClock, th.buildtopReset) {
         val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
         val uart_to_tsi = Module(new UARTToTSI(freq))
         ram.module.io.tsi_ser.flipConnect(uart_to_tsi.io.serial)
-        th.asInstanceOf[Arty100THarness].io_uart_bb.bundle <> uart_to_tsi.io.uart
+
+        ath.io_uart_bb.bundle <> uart_to_tsi.io.uart
+        ath.other_leds(1) := uart_to_tsi.io.serial.out.valid
+        ath.other_leds(2) := uart_to_tsi.io.serial.in.valid
+        ath.other_leds(3) := uart_to_tsi.io.uart.rxd
+        ath.other_leds(4) := uart_to_tsi.io.uart.txd
+
+        ath.other_leds(9) := ram.module.io.adapter_state(0)
+        ath.other_leds(10) := ram.module.io.adapter_state(1)
+        ath.other_leds(11) := ram.module.io.adapter_state(2)
+        ath.other_leds(12) := ram.module.io.adapter_state(3)
       }
     })
   }

generators/chipyard/src/main/scala/Subsystem.scala

@@ -62,6 +62,9 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
     val intSink = IntSinkNode(IntSinkPortSimple())
     intSink := intNexus :=* ibus.toPLIC
 
+    // avoids a bug when there are no interrupt sources
+    ibus.fromAsync := NullIntSource()
+
     // Need to have at least 1 driver to the tile notification sinks
     tileHaltXbarNode := IntSourceNode(IntSourcePortSimple())
     tileWFIXbarNode := IntSourceNode(IntSourcePortSimple())