[ci skip] Re-add suggestName for axi4 mmio mem

2023-10-13 17:36:41 -07:00
parent deab3b11b6
commit 6bd2e9dddb
1 changed files with 1 additions and 1 deletions
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -135,7 +135,7 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends HarnessBinder({
 class WithSimAXIMMIO extends HarnessBinder({
  case (th: HasHarnessInstantiators, port: AXI4MMIOPort) => {
    val mmio_mem = LazyModule(new SimAXIMem(port.edge, size = port.params.size)(Parameters.empty))
-    withClock(port.io.clock) { Module(mmio_mem.module) }
+    withClock(port.io.clock) { Module(mmio_mem.module).suggestName("mmio_mem") }
    mmio_mem.io_axi4.head <> port.io.bits
  }
 })