wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Initial CIRCT integration [ci skip]

Browse Source
This commit is contained in:
abejgonzalez
2022-10-04 08:12:48 -07:00
committed by joey0320
parent 4b60db6f8e
commit 873131c0c7
2 changed files with 42 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
common.mk
View File

@@ -110,6 +110,15 @@ $(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_D
--top-module $(MODEL_PACKAGE).$(MODEL) \
--legacy-configs $(CONFIG_PACKAGE):$(CONFIG) \
$(EXTRA_CHISEL_OPTIONS))
sed -i '1d' $(ANNO_FILE)
echo "[" >> t.json
echo "{" >> t.json
echo " \"class\": \"sifive.enterprise.firrtl.ModuleHierarchyAnnotation\"," >> t.json
echo " \"filename\": \"./mod-he.json\"" >> t.json
echo "}," >> t.json
mv $(ANNO_FILE) t2.json
cat t.json t2.json > $(ANNO_FILE)
rm t.json t2.json
.PHONY: firrtl
firrtl: $(FIRRTL_FILE)
@@ -117,11 +126,7 @@ firrtl: $(FIRRTL_FILE)
#########################################################################################
# create verilog files rules and variables
#########################################################################################
REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF)
HARNESS_CONF_FLAGS = -thconf $(HARNESS_SMEMS_CONF)
TOP_TARGETS = $(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes)
HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes)
CIRCT_TARGETS = $(VSRC_SMEMS_FILE) $(VSRC_MODH_JSON)
# DOC include start: FirrtlCompiler
$(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
@@ -145,6 +150,32 @@ $(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
--log-level $(FIRRTL_LOGLEVEL) \
$(EXTRA_FIRRTL_OPTIONS))
touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
# NOTE: These *_temp intermediate targets will get removed in favor of make 4.3 grouped targets (&: operator)
.INTERMEDIATE: firrtl_temp
$(CIRCT_TARGETS): firrtl_temp
@echo "" > /dev/null
firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
$(SCRATCH_HOME)/circt/build/bin/firtool \
--export-module-hierarchy \
--emit-metadata \
--format=fir \
-warn-on-unprocessed-annotations \
-verify-each=false \
-dedup \
--annotation-file=$(ANNO_FILE) \
--disable-annotation-classless \
--disable-annotation-unknown \
--lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \
--repl-seq-mem \
--repl-seq-mem-circuit=$(MODEL) \
--repl-seq-mem-file=$(VSRC_SMEMS_FILE) \
--split-verilog \
-o $(VSRC_DUMP) \
$(FIRRTL_FILE)
# touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
>>>>>>> 9306c549 (Initial CIRCT integration [ci skip])
# DOC include end: FirrtlCompiler
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs

10
variables.mk
View File

@@ -146,6 +146,10 @@ endif
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
VSRC_DUMP ?= $(build_dir)/vsrc
VSRC_SMEMS_FILE ?= $(VSRC_DUMP)/$(long_name).mems.v
VSRC_MODH_JSON ?= $(VSRC_DUMP)/mod-he.json
TOP_FILE ?= $(build_dir)/$(long_name).top.v
TOP_FIR ?= $(build_dir)/$(long_name).top.fir
TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json
@@ -240,10 +244,8 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
# sources needed to run simulators
#########################################################################################
sim_vsrcs = \
$(TOP_FILE) \
$(HARNESS_FILE) \
$(TOP_SMEMS_FILE) \
$(HARNESS_SMEMS_FILE)
$(VSRC_SMEMS_FILE) \
$(VSRC_MODH_JSON)
#########################################################################################
# assembly/benchmark variables