Add documentation page indicating existence of prefetchers

docs/Generators/Prefetchers.rst

@@ -0,0 +1,9 @@
+Prefetchers
+====================================
+
+The BAR-fetchers library is a collection of Chisel-implemented prefetchers, designed for compatibility with Chipyard and Rocket-Chip SoCs.
+This package implements a generic prefetcher API, and example implementations of NextLine, Strided, and AMPM prefetchers.
+
+Prefetchers can be instantiated in front of a L1D HellaCache, or as TileLink nodes in front of some TileLink bus.
+
+An example configuration using prefetchers is found in the ``PrefetchingRocketConfig``

docs/Generators/index.rst

@@ -34,3 +34,4 @@ so changes to the generators themselves will automatically be used when building
    NVDLA
    Sodor
    Mempress
+   Prefetchers

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -128,9 +128,9 @@ class CustomIOChipTopRocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class PrefetchingRocketConfig extends Config(
-  new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++   // strided prefetcher into L1D$
-  new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++             // next-line prefetcher into L2 for L1I$ accesses
-  new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++                // AMPM prefetcher into L2 for L1D$ accesses
+  new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++   // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$
+  new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++             // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2
+  new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++                // AMPM prefetcher, site between L1D$ and L2, monitors L1D$ misses to prefetch into L2
   new chipyard.config.WithTilePrefetchers ++                                           // add TL prefetchers between tiles and the sbus
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++                               // single rocket-core
   new chipyard.config.AbstractConfig)

scripts/tutorial-patches/build.sbt.patch

@@ -10,7 +10,7 @@ index ec36a85f..c0c2849a 100644
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
      dsptools, `rocket-dsp-utils`,
      gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
-     constellation, mempress)
+     constellation, mempress, barf)
 @@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
    .settings(libraryDependencies ++= rocketLibDeps.value)
    .settings(commonSettings)