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Add documentation page indicating existence of prefetchers

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This commit is contained in:
Jerry Zhao
2023-06-08 14:24:34 -07:00
parent 7cbabaa18a
commit 903971f32f
4 changed files with 14 additions and 4 deletions
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9
docs/Generators/Prefetchers.rst Normal file
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@@ -0,0 +1,9 @@
Prefetchers
====================================
The BAR-fetchers library is a collection of Chisel-implemented prefetchers, designed for compatibility with Chipyard and Rocket-Chip SoCs.
This package implements a generic prefetcher API, and example implementations of NextLine, Strided, and AMPM prefetchers.
Prefetchers can be instantiated in front of a L1D HellaCache, or as TileLink nodes in front of some TileLink bus.
An example configuration using prefetchers is found in the ``PrefetchingRocketConfig``

1
docs/Generators/index.rst
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@@ -34,3 +34,4 @@ so changes to the generators themselves will automatically be used when building
NVDLA NVDLA
Sodor Sodor
Mempress Mempress
Prefetchers

6
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -128,9 +128,9 @@ class CustomIOChipTopRocketConfig extends Config(
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
class PrefetchingRocketConfig extends Config( class PrefetchingRocketConfig extends Config(
new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher into L1D$ new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$
new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher into L2 for L1I$ accesses new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2
new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher into L2 for L1D$ accesses new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, site between L1D$ and L2, monitors L1D$ misses to prefetch into L2
new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)

2
scripts/tutorial-patches/build.sbt.patch
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@@ -10,7 +10,7 @@ index ec36a85f..c0c2849a 100644
+// sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsp-utils`, dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
constellation, mempress) constellation, mempress, barf)
@@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) @@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
.settings(libraryDependencies ++= rocketLibDeps.value) .settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings) .settings(commonSettings)