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Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.

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This commit is contained in:
James Dunn
2020-09-17 13:43:28 -07:00
parent 2580073d75
commit 9135cda959
2 changed files with 5 additions and 5 deletions
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2
fpga/src/main/scala/arty/TestHarness.scala
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@@ -26,7 +26,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
val harnessClock = clock_32MHz
val harnessReset = hReset
val success = false.B
val dutReset = hReset
val dutReset = reset_core
// must be after HasHarnessSignalReferences assignments
ldut.harnessFunctions.foreach(_(this))

8
fpga/src/main/scala/arty/e300/IOBinders.scala
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@@ -56,10 +56,8 @@ class WithE300Connections extends OverrideIOBinder({
val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset")
val io_ndreset = IO(Output(Bool())).suggestName("ndreset")
// This needs to be de-asserted synchronously to the coreClk.
val async_corerst = system.aon.rsts.corerst
// Add in debug-controlled reset.
system.reset := ResetCatchAndSync(system.clock, async_corerst, 20)
val io_async_corerst = IO(Input(Bool())).suggestName("core_reset")
system.reset := ResetCatchAndSync(system.clock, io_async_corerst, 20)
Debug.connectDebugClockAndReset(system.debug, system.clock)
//-----------------------------------------------------------------------
@@ -186,6 +184,8 @@ class WithE300Connections extends OverrideIOBinder({
val harnessFn = (baseTh: HasHarnessSignalReferences) => {
baseTh match { case th: ArtyShell =>
io_async_corerst := th.reset_core
//-----------------------------------------------------------------------
// Clock divider
//-----------------------------------------------------------------------