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Fix missing childClock/childReset in Arty100THarness

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This commit is contained in:
Jerry Zhao
2024-01-04 13:34:53 -08:00
committed by GitHub
parent d9bc036cb6
commit 9ab9132c8b
1 changed files with 3 additions and 0 deletions
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3
fpga/src/main/scala/arty100t/Harness.scala
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@@ -76,6 +76,9 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
def referenceReset = dutClock.in.head._1.reset def referenceReset = dutClock.in.head._1.reset
def success = { require(false, "Unused"); false.B } def success = { require(false, "Unused"); false.B }
childClock := harnessBinderClock
childReset := harnessBinderReset
ddrOverlay.mig.module.clock := harnessBinderClock ddrOverlay.mig.module.clock := harnessBinderClock
ddrOverlay.mig.module.reset := harnessBinderReset ddrOverlay.mig.module.reset := harnessBinderReset
ddrBlockDuringReset.module.clock := harnessBinderClock ddrBlockDuringReset.module.clock := harnessBinderClock