fully switch to chisel3

This commit is contained in:
Howard Mao
2017-02-07 17:33:38 -08:00
parent 41f439a2c3
commit 9ed41fc3dc
4 changed files with 21 additions and 21 deletions

View File

@@ -4,13 +4,13 @@ import util.GeneratorApp
import diplomacy.LazyModule
import rocketchip._
import testchipip._
import Chisel._
import chisel3._
import cde.Parameters
class TestHarness(implicit val p: Parameters) extends Module {
val io = new Bundle {
val success = Bool(OUTPUT)
}
val io = IO(new Bundle {
val success = Output(Bool())
})
def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop(p))

View File

@@ -9,12 +9,12 @@ import diplomacy._
import rocketchip._
class PWMBase extends Module {
val io = new Bundle {
val pwmout = Bool(OUTPUT)
val period = UInt(INPUT, 64)
val duty = UInt(INPUT, 64)
val enable = Bool(INPUT)
}
val io = IO(new Bundle {
val pwmout = Output(Bool())
val period = Input(UInt(64.W))
val duty = Input(UInt(64.W))
val enable = Input(Bool())
})
// The counter should count up until period is reached
val counter = Reg(UInt(width = 64))
@@ -31,10 +31,10 @@ class PWMBase extends Module {
}
class PWMTL(implicit p: Parameters) extends Module {
val io = new Bundle {
val pwmout = Bool(OUTPUT)
val tl = new ClientUncachedTileLinkIO().flip
}
val io = IO(new Bundle {
val pwmout = Output(Bool())
val tl = Flipped(new ClientUncachedTileLinkIO())
})
// How many clock cycles in a PWM cycle?
val period = Reg(UInt(width = 64))
@@ -95,10 +95,10 @@ class PWMTL(implicit p: Parameters) extends Module {
}
class PWMAXI(implicit p: Parameters) extends Module {
val io = new Bundle {
val pwmout = Bool(OUTPUT)
val axi = new NastiIO().flip
}
val io = IO(new Bundle {
val pwmout = Output(Bool())
val axi = Flipped(new NastiIO())
})
// How many clock cycles in a PWM cycle?
val period = Reg(UInt(width = 64))
@@ -158,7 +158,7 @@ trait PeripheryPWM extends LazyModule {
}
trait PeripheryPWMBundle {
val pwmout = Bool(OUTPUT)
val pwmout = Output(Bool())
}
case object BuildPWM extends Field[(ClientUncachedTileLinkIO, Parameters) => Bool]