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Merge branch 'main' of https://github.com/ucb-bar/chipyard into ucb-bar-main

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This commit is contained in:
Richard Yan
2024-05-15 23:22:20 -07:00
parent eab9eabf98 e2f4ea6814
commit a18c5de271
142 changed files with 3775 additions and 9699 deletions
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14
.github/scripts/check-commit.sh vendored
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@@ -45,21 +45,11 @@ search () {
done
}
submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
dir="generators"
branches=("master" "main" "dev")
search
submodules=("esp-tools-feedstock")
dir="toolchains/esp-tools"
branches=("main")
search
submodules=("riscv-isa-sim" "riscv-pk" "riscv-tests")
dir="toolchains/esp-tools"
branches=("master")
search
submodules=("riscv-tools-feedstock")
dir="toolchains/riscv-tools"
branches=("main")
@@ -92,7 +82,7 @@ dir="software"
branches=("master" "dev")
search
submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde")
submodules=("DRAMSim2" "axe" "dsptools" "dsptools-chisel3" "rocket-dsp-utils" "torture" "fixedpoint" "fixedpoint-chisel3" "cde" "midas-targetutils")
dir="tools"
branches=("master" "dev" "main")
search

8
.github/scripts/defaults.sh vendored
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@@ -30,7 +30,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-gpu"]="chipyard-radiance chipyard-radiance-fuzzer chipyard-coalescer coalescer"
grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
@@ -41,7 +41,6 @@ grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
declare -A mapping
mapping["chipyard-rocket"]=" CONFIG=QuadChannelRocketConfig"
mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig"
mapping["chipyard-prefetchers"]=" CONFIG=PrefetchingRocketConfig"
mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
@@ -53,7 +52,6 @@ mapping["chipyard-dmiboomv3"]=" CONFIG=dmiMediumBoomV3CosimConfig"
mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig"
mapping["chipyard-dmiboomv4"]=" CONFIG=dmiMediumBoomV4CosimConfig"
mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
@@ -81,8 +79,8 @@ mapping["chipyard-coalescer"]=" CONFIG=MemtraceCoreConfig"
mapping["constellation"]=" SUB_PROJECT=constellation"
mapping["coalescer"]=" SUB_PROJECT=coalescer"
mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig"
mapping["fireboom"]="TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig"
mapping["icenet"]="SUB_PROJECT=icenet"
mapping["testchipip"]="SUB_PROJECT=testchipip"
mapping["rocketchip-amba"]="SUB_PROJECT=rocketchip CONFIG=AMBAUnitTestConfig"

2
.github/scripts/remote-do-rtl-build.sh vendored
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@@ -53,5 +53,5 @@ do
export COURSIER_CACHE=$REMOTE_COURSIER_CACHE
export JVM_MEMORY=10G
export JAVA_TMP_DIR=$REMOTE_JAVA_TMP_DIR
make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info ${mapping[$key]}
make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR ${mapping[$key]}
done

10
.github/scripts/remote-run-firesim-scala-tests.sh vendored
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@@ -13,10 +13,8 @@ source $SCRIPT_DIR/defaults.sh
cd $REMOTE_CHIPYARD_DIR
./scripts/init-submodules-no-riscv-tools.sh
# Run Firesim Scala Tests
# Test firesim compile and metasim
export FIRESIM_ENV_SOURCED=1
export COURSIER_CACHE=$REMOTE_COURSIER_CACHE
export JVM_MEMORY=10G
export JAVA_TMP_DIR=$REMOTE_JAVA_TMP_DIR
export TEST_DISABLE_VIVADO=1
make -C $REMOTE_FIRESIM_DIR TARGET_SBT_PROJECT="{file:$REMOTE_CHIPYARD_DIR}firechip" testOnly ${mapping[$1]}
cd $REMOTE_FIRESIM_DIR
make TARGET_PROJECT=firesim EMUL=verilator ${mapping[$1]} run-verilator SIM_BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple

7
.github/scripts/run-tests.sh vendored
View File

@@ -77,9 +77,6 @@ case $1 in
rocketchip)
run_bmark
;;
chipyard-hwacha)
make run-rv64uv-p-asm-tests -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS
;;
chipyard-gemmini)
GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests
rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests
@@ -88,10 +85,6 @@ case $1 in
run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal
run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal
;;
chipyard-sha3)
(cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh)
run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/sha3/software/tests/bare/sha3-rocc.riscv
;;
chipyard-mempress)
(cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make)
run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv

18
.github/workflows/chipyard-full-flow.yml vendored
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@@ -61,8 +61,8 @@ jobs:
- '**/.gitignore'
- '.github/ISSUE_TEMPLATE/**'
setup-repo:
name: setup-repo
full-flow:
name: full-flow
needs: [change-filters, cancel-prior-workflows]
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: as4
@@ -84,12 +84,6 @@ jobs:
mkdir ${{ env.JAVA_TMP_DIR }}
export MAKEFLAGS="-j32"
./build-setup.sh -v
run-cfg-finder:
name: run-cfg-finder
needs: [setup-repo]
runs-on: as4
steps:
- name: Run config finder
run: |
cd ${{ env.REMOTE_WORK_DIR }}
@@ -97,12 +91,6 @@ jobs:
source env.sh
cd sims/verilator
make find-config-fragments
run-tutorial:
name: run-tutorial
needs: [setup-repo]
runs-on: as4
steps:
- name: Run smoke test
run: |
cd ${{ env.REMOTE_WORK_DIR }}
@@ -169,7 +157,7 @@ jobs:
cleanup:
name: cleanup
needs: [run-tutorial]
needs: [full-flow]
runs-on: as4
if: ${{ always() }}
steps:

48
.github/workflows/chipyard-run-tests.yml vendored
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@@ -119,29 +119,6 @@ jobs:
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
.github/scripts/check-commit.sh
tutorial-setup-check:
name: tutorial-setup-check
needs: [setup-complete]
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Check that the tutorial-setup patches apply
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
scripts/tutorial-setup.sh
documentation-check:
name: documentation-check
needs: [setup-complete]
@@ -800,29 +777,6 @@ jobs:
group-key: "group-peripherals"
project-key: "chipyard-llcchiplet"
chipyard-sha3-run-tests:
name: chipyard-sha3-run-tests
needs: prepare-chipyard-accels
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-sha3"
chipyard-gemmini-run-tests:
name: chipyard-gemmini-run-tests
needs: prepare-chipyard-accels
@@ -1172,7 +1126,6 @@ jobs:
all_tests_passed:
name: "all tests passed"
needs: [commit-on-master-check,
tutorial-setup-check,
documentation-check,
chipyard-rocket-run-tests,
chipyard-hetero-run-tests,
@@ -1190,7 +1143,6 @@ jobs:
chipyard-tethered-run-tests,
chipyard-symmetric-run-tests,
chipyard-llcchiplet-run-tests,
chipyard-sha3-run-tests,
chipyard-gemmini-run-tests,
chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
chipyard-prefetchers-run-tests,

250
.gitmodules vendored
View File

@@ -1,137 +1,125 @@
[submodule "generators/rocket-chip"]
path = generators/rocket-chip
url = https://github.com/hansungk/rocket-chip.git
[submodule "generators/testchipip"]
path = generators/testchipip
url = https://github.com/richardyrh/testchipip.git
[submodule "tools/barstools"]
path = tools/barstools
url = https://github.com/ucb-bar/barstools.git
[submodule "tools/torture"]
path = tools/torture
url = https://github.com/ucb-bar/riscv-torture.git
[submodule "fpga/fpga-shells"]
path = fpga/fpga-shells
url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
[submodule "generators/bar-fetchers"]
path = generators/bar-fetchers
url = https://github.com/ucb-bar/bar-fetchers.git
[submodule "generators/boom"]
path = generators/boom
url = https://github.com/riscv-boom/riscv-boom.git
[submodule "generators/hwacha"]
path = generators/hwacha
url = https://github.com/ucb-bar/hwacha.git
[submodule "sims/firesim"]
path = sims/firesim
url = https://github.com/firesim/firesim.git
[submodule "generators/icenet"]
path = generators/icenet
url = https://github.com/firesim/icenet.git
[submodule "tools/circt"]
path = tools/circt
url = https://github.com/llvm/circt.git
[submodule "tools/dsptools"]
path = tools/dsptools
url = https://github.com/ucb-bar/dsptools.git
[submodule "generators/sha3"]
path = generators/sha3
url = https://github.com/ucb-bar/sha3.git
[submodule "vlsi/hammer-mentor-plugins"]
path = vlsi/hammer-mentor-plugins
url = https://github.com/ucb-bar/hammer-mentor-plugins.git
[submodule "tools/axe"]
path = tools/axe
url = https://github.com/CTSRD-CHERI/axe.git
[submodule "software/spec2017"]
path = software/spec2017
url = https://github.com/ucb-bar/spec2017-workload.git
[submodule "software/coremark"]
path = software/coremark
url = https://github.com/ucb-bar/coremark-workload.git
[submodule "generators/gemmini"]
path = generators/gemmini
url = https://github.com/ucb-bar/gemmini
[submodule "software/firemarshal"]
path = software/firemarshal
url = https://github.com/firesim/FireMarshal.git
[submodule "generators/caliptra-aes-acc"]
path = generators/caliptra-aes-acc
url = https://github.com/ucb-bar/caliptra-aes-acc.git
[submodule "generators/constellation"]
path = generators/constellation
url = https://github.com/ucb-bar/constellation.git
[submodule "generators/cva6"]
path = generators/cva6
url = https://github.com/ucb-bar/cva6-wrapper.git
[submodule "generators/diplomacy"]
path = generators/diplomacy
url = https://github.com/chipsalliance/diplomacy.git
[submodule "tools/DRAMSim2"]
path = tools/DRAMSim2
url = https://github.com/firesim/DRAMSim2.git
[submodule "generators/nvdla"]
path = generators/nvdla
url = https://github.com/ucb-bar/nvdla-wrapper.git
[submodule "software/nvdla-workload"]
path = software/nvdla-workload
url = https://github.com/ucb-bar/nvdla-workload.git
[submodule "software/baremetal-ide"]
path = software/baremetal-ide
url = https://github.com/ucb-bar/Baremetal-IDE.git
[submodule "generators/riscv-sodor"]
path = generators/riscv-sodor
url = https://github.com/ucb-bar/riscv-sodor.git
[submodule "fpga/fpga-shells"]
path = fpga/fpga-shells
url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
[submodule "tools/rocket-dsp-utils"]
path = tools/rocket-dsp-utils
url = https://github.com/ucb-bar/rocket-dsp-utils
[submodule "generators/ibex"]
path = generators/ibex
url = https://github.com/ucb-bar/ibex-wrapper
[submodule "generators/fft-generator"]
path = generators/fft-generator
url = https://github.com/ucb-bar/FFTGenerator.git
[submodule "toolchains/riscv-tools/riscv-tests"]
path = toolchains/riscv-tools/riscv-tests
url = https://github.com/riscv-software-src/riscv-tests.git
[submodule "toolchains/riscv-tools/riscv-pk"]
path = toolchains/riscv-tools/riscv-pk
url = https://github.com/riscv-software-src/riscv-pk.git
[submodule "toolchains/riscv-tools/riscv-openocd"]
path = toolchains/riscv-tools/riscv-openocd
url = https://github.com/riscv/riscv-openocd.git
[submodule "toolchains/riscv-tools/riscv-isa-sim"]
path = toolchains/riscv-tools/riscv-isa-sim
url = https://github.com/richardyrh/riscv-isa-sim
[submodule "toolchains/riscv-tools/riscv-tools-feedstock"]
path = toolchains/riscv-tools/riscv-tools-feedstock
url = https://github.com/ucb-bar/riscv-tools-feedstock.git
[submodule "toolchains/esp-tools/esp-tools-feedstock"]
path = toolchains/esp-tools/esp-tools-feedstock
url = https://github.com/ucb-bar/esp-tools-feedstock.git
[submodule "toolchains/esp-tools/riscv-isa-sim"]
path = toolchains/esp-tools/riscv-isa-sim
url = https://github.com/ucb-bar/esp-isa-sim.git
[submodule "toolchains/esp-tools/riscv-pk"]
path = toolchains/esp-tools/riscv-pk
url = https://github.com/riscv-software-src/riscv-pk.git
[submodule "toolchains/esp-tools/riscv-tests"]
path = toolchains/esp-tools/riscv-tests
url = https://github.com/ucb-bar/esp-tests.git
[submodule "toolchains/libgloss"]
path = toolchains/libgloss
url = https://github.com/ucb-bar/libgloss-htif.git
[submodule "generators/constellation"]
path = generators/constellation
url = https://github.com/ucb-bar/constellation.git
[submodule "generators/gemmini"]
path = generators/gemmini
url = https://github.com/ucb-bar/gemmini.git
[submodule "generators/hardfloat"]
path = generators/hardfloat
url = https://github.com/ucb-bar/berkeley-hardfloat.git
[submodule "generators/ibex"]
path = generators/ibex
url = https://github.com/ucb-bar/ibex-wrapper.git
[submodule "generators/icenet"]
path = generators/icenet
url = https://github.com/firesim/icenet.git
[submodule "generators/mempress"]
path = generators/mempress
url = https://github.com/ucb-bar/mempress.git
[submodule "tools/cde"]
path = tools/cde
url = https://github.com/chipsalliance/cde.git
[submodule "generators/nvdla"]
path = generators/nvdla
url = https://github.com/ucb-bar/nvdla-wrapper.git
[submodule "generators/riscv-sodor"]
path = generators/riscv-sodor
url = https://github.com/ucb-bar/riscv-sodor.git
[submodule "generators/rocc-acc-utils"]
path = generators/rocc-acc-utils
url = https://github.com/ucb-bar/rocc-acc-utils.git
[submodule "generators/rocket-chip"]
path = generators/rocket-chip
url = https://github.com/hansungk/rocket-chip.git
[submodule "generators/rocket-chip-blocks"]
path = generators/rocket-chip-blocks
url = https://github.com/chipsalliance/rocket-chip-blocks.git
[submodule "generators/rocket-chip-inclusive-cache"]
path = generators/rocket-chip-inclusive-cache
url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "generators/shuttle"]
path = generators/shuttle
url = https://github.com/ucb-bar/shuttle.git
[submodule "generators/testchipip"]
path = generators/testchipip
url = https://github.com/richardyrh/testchipip.git
[submodule "sims/firesim"]
path = sims/firesim
url = https://github.com/firesim/firesim.git
[submodule "software/baremetal-ide"]
path = software/baremetal-ide
url = https://github.com/ucb-bar/Baremetal-IDE.git
[submodule "software/coremark"]
path = software/coremark
url = https://github.com/ucb-bar/coremark-workload.git
[submodule "software/embench/embench-iot"]
path = software/embench/embench-iot
url = https://github.com/embench/embench-iot.git
[submodule "shuttle"]
path = generators/shuttle
url = https://github.com/ucb-bar/shuttle.git
[submodule "generators/bar-fetchers"]
path = generators/bar-fetchers
url = https://github.com/ucb-bar/bar-fetchers.git
[submodule "tools/fixedpoint"]
path = tools/fixedpoint
[submodule "software/firemarshal"]
path = software/firemarshal
url = https://github.com/firesim/FireMarshal.git
[submodule "software/nvdla-workload"]
path = software/nvdla-workload
url = https://github.com/ucb-bar/nvdla-workload.git
[submodule "software/spec2017"]
path = software/spec2017
url = https://github.com/ucb-bar/spec2017-workload.git
[submodule "toolchains/libgloss"]
path = toolchains/libgloss
url = https://github.com/ucb-bar/libgloss-htif.git
[submodule "toolchains/riscv-tools/riscv-isa-sim"]
path = toolchains/riscv-tools/riscv-isa-sim
url = https://github.com/richardyrh/riscv-isa-sim
[submodule "toolchains/riscv-tools/riscv-openocd"]
path = toolchains/riscv-tools/riscv-openocd
url = https://github.com/riscv/riscv-openocd.git
[submodule "toolchains/riscv-tools/riscv-pk"]
path = toolchains/riscv-tools/riscv-pk
url = https://github.com/riscv-software-src/riscv-pk.git
[submodule "toolchains/riscv-tools/riscv-spike-devices"]
path = toolchains/riscv-tools/riscv-spike-devices
url = https://github.com/ucb-bar/spike-devices.git
[submodule "toolchains/riscv-tools/riscv-tests"]
path = toolchains/riscv-tools/riscv-tests
url = https://github.com/riscv-software-src/riscv-tests.git
[submodule "toolchains/riscv-tools/riscv-tools-feedstock"]
path = toolchains/riscv-tools/riscv-tools-feedstock
url = https://github.com/ucb-bar/riscv-tools-feedstock.git
[submodule "tools/DRAMSim2"]
path = tools/DRAMSim2
url = https://github.com/firesim/DRAMSim2.git
[submodule "tools/axe"]
path = tools/axe
url = https://github.com/CTSRD-CHERI/axe.git
[submodule "tools/cde"]
path = tools/cde
url = https://github.com/chipsalliance/cde.git
[submodule "tools/circt"]
path = tools/circt
url = https://github.com/llvm/circt.git
[submodule "tools/dsptools-fixedpoint"]
path = tools/dsptools-chisel3
url = https://github.com/ucb-bar/dsptools.git
[submodule "tools/fixedpoint-chisel3"]
path = tools/fixedpoint-chisel3
url = https://github.com/ucb-bar/fixedpoint.git
[submodule "generators/hardfloat"]
path = generators/hardfloat
@@ -144,16 +132,26 @@
url = https://github.com/ucb-bar/rocc-acc-utils
[submodule "tools/install-circt"]
path = tools/install-circt
url = https://github.com/circt/install-circt/
[submodule "toolchains/riscv-tools/riscv-spike-devices"]
path = toolchains/riscv-tools/riscv-spike-devices
url = https://github.com/ucb-bar/spike-devices.git
[submodule "generators/rocket-chip-blocks"]
path = generators/rocket-chip-blocks
url = https://github.com/chipsalliance/rocket-chip-blocks.git
[submodule "generators/rocket-chip-inclusive-cache"]
path = generators/rocket-chip-inclusive-cache
url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
url = https://github.com/circt/install-circt.git
[submodule "tools/rocket-dsp-utils"]
path = tools/rocket-dsp-utils
url = https://github.com/ucb-bar/rocket-dsp-utils.git
[submodule "tools/torture"]
path = tools/torture
url = https://github.com/ucb-bar/riscv-torture.git
[submodule "vlsi/hammer-mentor-plugins"]
path = vlsi/hammer-mentor-plugins
url = https://github.com/ucb-bar/hammer-mentor-plugins.git
[submodule "tools/dsptools"]
path = tools/dsptools
url = https://github.com/ucb-bar/dsptools.git
[submodule "tools/fixedpoint"]
path = tools/fixedpoint
url = https://github.com/ucb-bar/fixedpoint.git
[submodule "tools/midas-targetutils"]
path = tools/midas-targetutils
url = https://github.com/firesim/midas-targetutils.git
[submodule "generators/radiance"]
path = generators/radiance
url = https://github.com/ucb-bar/radiance.git

4
README.md
View File

@@ -16,7 +16,7 @@ To get started using Chipyard, see the stable documentation on the Chipyard docu
Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
@@ -65,7 +65,6 @@ These additional publications cover many of the internal components used in Chip
* **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://old.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf).
* **SonicBOOM (BOOMv3)**: J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf).
* **COBRA (BOOM Branch Prediction)**: J. Zhao, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408173).
* **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf).
* **Gemmini**: H. Genc, et al., *DAC'21*. [PDF](https://arxiv.org/pdf/1911.09925).
* **Sims**
* **FireSim**: S. Karandikar, et al., *ISCA'18*. [PDF](https://sagark.org/assets/pubs/firesim-isca2018.pdf).
@@ -87,7 +86,6 @@ These additional publications cover many of the internal components used in Chip
This work is supported by the NSF CCRI ENS Chipyard Award #2016662.
[hwacha]:https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.pdf
[hammer]:https://github.com/ucb-bar/hammer
[firesim]:https://fires.im
[ucb-bar]: http://bar.eecs.berkeley.edu

120
build.sbt
View File

@@ -1,5 +1,9 @@
import Tests._
val chisel6 = sys.env.get("USE_CHISEL6").isDefined
val chiselTestVersion = if (chisel6) "6.0.0" else "0.6.0"
val scalaVersionFromChisel = if (chisel6) "2.13.12" else "2.13.10"
// This gives us a nicer handle to the root project instead of using the
// implicit one
lazy val chipyardRoot = Project("chipyardRoot", file("."))
@@ -11,7 +15,7 @@ val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
case p: Project => p.name
case l: Library => l.moduleCoord.name
}
if (Seq("firrtl", "chisel3").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version
if (Seq("firrtl", "chisel3", "chisel").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version
dep.target
} else {
"renamed/" + dep.target
@@ -21,11 +25,13 @@ val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
lazy val commonSettings = Seq(
organization := "edu.berkeley.cs",
version := "1.6",
scalaVersion := "2.13.10",
scalaVersion := scalaVersionFromChisel,
assembly / test := {},
assembly / assemblyMergeStrategy := {
case PathList("chisel3", "stage", xs @ _*) => chiselFirrtlMergeStrategy
case PathList("chisel", "stage", xs @ _*) => chiselFirrtlMergeStrategy
case PathList("firrtl", "stage", xs @ _*) => chiselFirrtlMergeStrategy
case PathList("META-INF", _*) => MergeStrategy.discard
// should be safe in JDK11: https://stackoverflow.com/questions/54834125/sbt-assembly-deduplicate-module-info-class
case x if x.endsWith("module-info.class") => MergeStrategy.discard
case x =>
@@ -35,6 +41,7 @@ lazy val commonSettings = Seq(
scalacOptions ++= Seq(
"-deprecation",
"-unchecked",
"-Ytasty-reader",
"-Ymacro-annotations"), // fix hierarchy API
unmanagedBase := (chipyardRoot / unmanagedBase).value,
allDependencies := {
@@ -44,6 +51,9 @@ lazy val commonSettings = Seq(
dropDeps.contains((dep.organization, dep.name))
}
},
libraryDependencies += "com.lihaoyi" %% "sourcecode" % "0.3.1",
libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
exportJars := true,
resolvers ++= Seq(
Resolver.sonatypeRepo("snapshots"),
@@ -82,13 +92,22 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
new Group(test.name, Seq(test), SubProcess(options))
} toSeq
val chiselVersion = "3.6.0"
lazy val chiselSettings = Seq(
libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
"org.apache.commons" % "commons-lang3" % "3.12.0",
"org.apache.commons" % "commons-text" % "1.9"),
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full))
lazy val chisel6Settings = Seq(
libraryDependencies ++= Seq("org.chipsalliance" %% "chisel" % "6.0.0"),
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.0.0" cross CrossVersion.full)
)
lazy val chisel3Settings = Seq(
libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.0"),
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full)
)
lazy val chiselSettings = (if (chisel6) chisel6Settings else chisel3Settings) ++ Seq(
libraryDependencies ++= Seq(
"org.apache.commons" % "commons-lang3" % "3.12.0",
"org.apache.commons" % "commons-text" % "1.9"
)
)
// Subproject definitions begin
@@ -97,8 +116,8 @@ lazy val chiselSettings = Seq(
lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
.settings(chiselSettings)
.dependsOn(midasTargetUtils)
.settings(commonSettings)
.dependsOn(if (chisel6) midasStandaloneTargetUtils else midasTargetUtils)
.settings(
libraryDependencies ++= Seq(
"org.scalatest" %% "scalatest" % "3.2.0" % "test"
@@ -109,7 +128,6 @@ lazy val rocketMacros = (project in rocketChipDir / "macros")
.settings(commonSettings)
.settings(
libraryDependencies ++= Seq(
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
)
)
@@ -118,11 +136,6 @@ lazy val diplomacy = freshProject("diplomacy", file("generators/diplomacy/diplom
.settings(commonSettings)
.settings(chiselSettings)
.settings(Compile / scalaSource := baseDirectory.value / "diplomacy")
.settings(
libraryDependencies ++= Seq(
"com.lihaoyi" %% "sourcecode" % "0.3.1"
)
)
lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
.dependsOn(hardfloat, rocketMacros, diplomacy, cde)
@@ -131,18 +144,11 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
.settings(
libraryDependencies ++= Seq(
"com.lihaoyi" %% "mainargs" % "0.5.0",
"org.scala-lang" % "scala-reflect" % scalaVersion.value,
"org.json4s" %% "json4s-jackson" % "4.0.5",
"org.scalatest" %% "scalatest" % "3.2.0" % "test",
"org.scala-graph" %% "graph-core" % "1.13.5",
"com.lihaoyi" %% "sourcecode" % "0.3.1"
"org.scala-graph" %% "graph-core" % "1.13.5"
)
)
.settings( // Settings for scalafix
semanticdbEnabled := true,
semanticdbVersion := scalafixSemanticdb.revision,
scalacOptions += "-Ywarn-unused"
)
lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
@@ -150,19 +156,23 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
// Contains annotations & firrtl passes you may wish to use in rocket-chip without
// introducing a circular dependency between RC and MIDAS
lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
lazy val midasTargetUtils = (project in file ("sims/firesim/sim/midas/targetutils"))
.settings(commonSettings)
.settings(chiselSettings)
lazy val midasStandaloneTargetUtils = (project in file("tools/midas-targetutils"))
.settings(commonSettings)
.settings(chiselSettings)
lazy val testchipip = (project in file("generators/testchipip"))
.dependsOn(rocketchip, rocketchip_blocks)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
val stageDir = if (chisel6) "tools/stage/src/main/scala" else "tools/stage-chisel3/src/main/scala"
lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
radiance,
sha3, // On separate line to allow for cleaner tutorial-setup patches
.dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
dsptools, rocket_dsp_utils,
gemmini, icenet, tracegen, cva6, nvdla, radiance, sodor, ibex, fft_generator,
radiance, gemmini, icenet, tracegen, cva6, nvdla, radiance, sodor, ibex, fft_generator,
constellation, mempress, barf, shuttle, caliptra_aes)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(
@@ -170,10 +180,11 @@ lazy val chipyard = (project in file("generators/chipyard"))
"org.reflections" % "reflections" % "0.10.2"
)
)
.settings(commonSettings)
.settings(commonSettings)
.settings(Compile / unmanagedSourceDirectories += file(stageDir))
lazy val mempress = (project in file("generators/mempress"))
.dependsOn(rocketchip, midasTargetUtils)
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
@@ -202,11 +213,6 @@ lazy val icenet = (project in file("generators/icenet"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val hwacha = (project in file("generators/hwacha"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val boom = freshProject("boom", file("generators/boom"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
@@ -232,17 +238,12 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val sha3 = (project in file("generators/sha3"))
.dependsOn(rocketchip, midasTargetUtils)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val radiance = (project in file("generators/radiance"))
.dependsOn(rocketchip, gemmini)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val gemmini = (project in file("generators/gemmini"))
lazy val gemmini = freshProject("gemmini", file("generators/gemmini"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
@@ -253,7 +254,7 @@ lazy val nvdla = (project in file("generators/nvdla"))
.settings(commonSettings)
lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc"))
.dependsOn(rocketchip, rocc_acc_utils, testchipip, midasTargetUtils)
.dependsOn(rocketchip, rocc_acc_utils, testchipip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
@@ -262,25 +263,25 @@ lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "iocell")
lazy val tapeout = (project in file("./tools/tapeout/"))
.settings(chisel3Settings) // stuck on chisel3 and SFC
.settings(commonSettings)
.settings(scalaVersion := "2.13.10") // stuck on chisel3 2.13.10
.settings(libraryDependencies ++= Seq("com.typesafe.play" %% "play-json" % "2.9.2"))
val fixedpointDir = if (chisel6) "./tools/fixedpoint" else "./tools/fixedpoint-chisel3"
lazy val fixedpoint = freshProject("fixedpoint", file(fixedpointDir))
.settings(chiselSettings)
.settings(commonSettings)
lazy val tapeout = (project in file("./tools/barstools/"))
.settings(chiselSettings)
.settings(commonSettings)
lazy val fixedpoint = (project in file("./tools/fixedpoint/"))
.settings(chiselSettings)
.settings(commonSettings)
lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
val dsptoolsDir = if (chisel6) "./tools/dsptools" else "./tools/dsptools-chisel3"
lazy val dsptools = freshProject("dsptools", file(dsptoolsDir))
.dependsOn(fixedpoint)
.settings(
chiselSettings,
commonSettings,
libraryDependencies ++= Seq(
"edu.berkeley.cs" %% "chiseltest" % "0.6.0",
"edu.berkeley.cs" %% "chiseltest" % chiselTestVersion,
"org.scalatest" %% "scalatest" % "3.2.+" % "test",
"org.typelevel" %% "spire" % "0.18.0",
"org.scalanlp" %% "breeze" % "2.1.0",
@@ -310,8 +311,17 @@ lazy val rocketchip_inclusive_cache = (project in file("generators/rocket-chip-i
.settings(libraryDependencies ++= rocketLibDeps.value)
// Library components of FireSim
lazy val midas = ProjectRef(firesimDir, "midas")
lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
lazy val midas = (project in file ("sims/firesim/sim/midas"))
.dependsOn(rocketchip, midasTargetUtils)
.settings(libraryDependencies ++= Seq(
"org.scalatestplus" %% "scalacheck-1-14" % "3.1.3.0" % "test"))
.settings(commonSettings)
.settings(chiselSettings)
lazy val firesimLib = (project in file("sims/firesim/sim/firesim-lib"))
.dependsOn(midas, icenet, testchipip, rocketchip_blocks)
.settings(commonSettings)
.settings(chiselSettings)
lazy val firechip = (project in file("generators/firechip"))
.dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")

78
common.mk
View File

@@ -17,10 +17,8 @@ HELP_COMPILATION_VARIABLES += \
" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \
" EXTRA_SIM_OUT_NAME = additional suffix appended to the simulation .out log filename" \
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \
" EXTRA_BASE_FIRRTL_OPTIONS = additional options to pass to the Scala FIRRTL compiler" \
" MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \
" ASPECTS = comma separated list of Chisel aspect flows to run (e.x. chipyard.upf.ChipTopUPFAspect)"
@@ -91,12 +89,12 @@ CHECK_SUBMODULES_COMMAND = echo "Checking all submodules in generators/ are init
SCALA_EXT = scala
VLOG_EXT = sv v
CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src)
CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim/src sims/firesim/sim/firesim-lib sims/firesim/sim/midas fpga/fpga-shells fpga/src tools/stage tools/stage-chisel3)
CHIPYARD_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(SCALA_EXT))
CHIPYARD_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(VLOG_EXT))
BARSTOOLS_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/barstools)
BARSTOOLS_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(SCALA_EXT))
BARSTOOLS_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(VLOG_EXT))
TAPEOUT_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/tapeout)
TAPEOUT_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(SCALA_EXT))
TAPEOUT_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(VLOG_EXT))
# This assumes no SBT meta-build sources
SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools)
SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties
@@ -130,7 +128,7 @@ $(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEP
$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
# order only dependency between sbt runs needed to avoid concurrent sbt runs
$(TAPEOUT_CLASSPATH_TARGETS) &: $(BARSTOOLS_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(BARSTOOLS_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS)
$(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS)
mkdir -p $(dir $@)
$(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH))
@@ -164,20 +162,11 @@ define mfc_extra_anno_contents
}
]
endef
define sfc_extra_low_transforms_anno_contents
[
{
"class": "firrtl.stage.RunFirrtlTransformAnnotation",
"transform": "barstools.tapeout.transforms.ExtraLowTransforms"
}
]
endef
export mfc_extra_anno_contents
export sfc_extra_low_transforms_anno_contents
$(EXTRA_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE)
$(FINAL_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE)
echo "$$mfc_extra_anno_contents" > $(MFC_EXTRA_ANNO_FILE)
echo "$$sfc_extra_low_transforms_anno_contents" > $(SFC_EXTRA_ANNO_FILE)
jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(EXTRA_ANNO_FILE)
jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE)
.PHONY: firrtl
firrtl: $(FIRRTL_FILE) $(FINAL_ANNO_FILE)
@@ -195,30 +184,9 @@ SFC_MFC_TARGETS = \
$(MFC_BB_MODS_FILELIST) \
$(GEN_COLLATERAL_DIR)
SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket
# DOC include start: FirrtlCompiler
# There are two possible cases for this step. In the first case, SFC
# compiles Chisel to CHIRRTL, and MFC compiles CHIRRTL to Verilog. Otherwise,
# when custom FIRRTL transforms are included or if a Fixed type is used within
# the dut, SFC compiles Chisel to LowFIRRTL and MFC compiles it to Verilog.
# Users can indicate to the Makefile of custom FIRRTL transforms by setting the
# "ENABLE_CUSTOM_FIRRTL_PASS" variable.
#
# hack: lower to low firrtl if Fixed types are found
# hack: when using dontTouch, io.cpu annotations are not removed by SFC,
# hence we remove them manually by using jq before passing them to firtool
$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) &: $(FIRRTL_FILE)
ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
echo $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none) > $(SFC_LEVEL)
echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), "$(SFC_REPL_SEQ_MEM)",) > $(EXTRA_FIRRTL_OPTIONS)
else
echo low > $(SFC_LEVEL)
echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" "$(SFC_REPL_SEQ_MEM)" > $(EXTRA_FIRRTL_OPTIONS)
endif
$(MFC_LOWERING_OPTIONS):
mkdir -p $(dir $@)
ifeq (,$(ENABLE_YOSYS_FLOW))
@@ -227,29 +195,8 @@ else
echo "$(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays" > $@
endif
$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(SFC_LEVEL)
if [ $(shell cat $(SFC_LEVEL)) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $@; fi
if [ $(shell cat $(SFC_LEVEL)) = none ]; then cat $(EXTRA_ANNO_FILE) > $@; fi
touch $@
$(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX)
$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS)
$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS)
rm -rf $(GEN_COLLATERAL_DIR)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\
--no-dedup \
--output-file $(SFC_FIRRTL_BASENAME) \
--output-annotation-file $(SFC_ANNO_FILE) \
--target-dir $(GEN_COLLATERAL_DIR) \
--input-file $(FIRRTL_FILE) \
--annotation-file $(FINAL_ANNO_FILE) \
--log-level $(FIRRTL_LOGLEVEL) \
--allow-unrecognized-annotations \
-X $(shell cat $(SFC_LEVEL)) \
$(shell cat $(EXTRA_FIRRTL_OPTIONS)))
-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL
@if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json; fi
@if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi
@if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json && rm $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi
firtool \
--format=fir \
--export-module-hierarchy \
@@ -261,11 +208,10 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F
--lowering-options=$(shell cat $(MFC_LOWERING_OPTIONS)) \
--repl-seq-mem \
--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
--annotation-file=$(SFC_ANNO_FILE) \
--annotation-file=$(FINAL_ANNO_FILE) \
--split-verilog \
-o $(GEN_COLLATERAL_DIR) \
$(SFC_FIRRTL_FILE)
-mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) 2> /dev/null
$(FIRRTL_FILE)
$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it
# DOC include end: FirrtlCompiler
@@ -301,12 +247,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
TOP_MACROCOMPILER_MODE ?= --mode synflops
$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR)
MODEL_MACROCOMPILER_MODE = --mode synflops
$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR)
########################################################################################

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18
conda-reqs/esp-tools.yaml
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@@ -1,18 +0,0 @@
channels:
- ucb-bar
- conda-forge
- litex-hub
- nodefaults
platforms:
- linux-64
dependencies:
# https://conda-forge.org/feedstock-outputs/
# filterable list of all conda-forge packages
# https://conda-forge.org/#contribute
# instructions on adding a recipe
# https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
# documentation on package_spec syntax for constraining versions
- esp-tools==1.0.1 # from ucb-bar channel - https://github.com/ucb-bar/esp-tools-feedstock

4
docs/Advanced-Concepts/Resources.rst
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@@ -33,7 +33,3 @@ For example:
lazy val myAwesomeAccel = (project in file("generators/myAwesomeAccelFolder"))
.dependsOn(rocketchip)
.settings(commonSettings)
lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
.dependsOn(myAwesomeAccel)
.settings(commonSettings)

2
docs/Advanced-Concepts/Top-Testharness.rst
View File

@@ -25,6 +25,8 @@ The default standard ``ChipTop`` provides a mimimal, barebones template for ``IO
For tapeouts, integrating Analog IP, or other non-standard use cases, Chipyard supports specifying a custom ``ChipTop`` using the ``BuildTop`` key.
An example of a custom ChipTop which uses non-standard IOCells is provided in `generators/chipyard/src/main/scala/example/CustomChipTop.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/example/CustomChipTop.scala>`__
You can also specify a fully custom ChipTop that does not use any RocketChip or Chipyard SoC components. An example of this is provided in `generators/chipyard/src/main/scala/example/EmptyChipTop.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/example/EmptyChipTop.scala>`__. The ``EmptyChipTop`` example can be built with ``make CONFIG=EmptyChipTopConfig TOP=EmptyChipTop``.
System/DigitalTop
-------------------------

18
docs/Chipyard-Basics/Chipyard-Components.rst
View File

@@ -31,19 +31,9 @@ Processor Cores
Accelerators
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
**Hwacha**
A decoupled vector architecture co-processor.
Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model.
Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface.
See :ref:`Generators/Hwacha:Hwacha` for more information.
**Gemmini**
A matrix-multiply accelerator targeting neural-networks
**SHA3**
A fixed-function accelerator for the SHA3 hash function. This simple accelerator is used as a demonstration for some of the
Chipyard integration flows using the RoCC interface.
System Components:
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -79,9 +69,9 @@ Tools
FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation.
See :ref:`Tools/FIRRTL:FIRRTL` for more information.
**Barstools**
**Tapeout-Tools (Formerly Barstools)**
A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL.
See :ref:`Tools/Barstools:Barstools` for more information.
See :ref:`Tools/Tapeout-Tools:Tapeout-Tools` for more information.
**Dsptools**
A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC).
@@ -95,10 +85,6 @@ Toolchains
The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.).
Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the Chipyard framework.
**esp-tools**
A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension.
This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.)
Software
-------------------------------------------

10
docs/Chipyard-Basics/Initial-Repo-Setup.rst
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@@ -63,11 +63,7 @@ Start by checking out the proper Chipyard version. Run:
# note: this may not be the latest release if the documentation version != "stable"
git checkout |version|
Next run the following script to fully setup Chipyard with a specific toolchain.
There are two toolchains, one for normal RISC-V programs called ``riscv-tools`` which is the one needed for most Chipyard use-cases, and another for Hwacha called ``esp-tools``.
Run the following script based off which compiler you would like to use.
.. Note:: Prior versions of Chipyard recommended ``esp-tools`` for Gemmini development. Gemmini should now be used with the standard ``riscv-tools``.
Next run the following script to fully setup Chipyard with the ``riscv-tools`` toolchain.
.. Warning:: The following script will complete a "full" installation of Chipyard which may take a long time depending on the system.
Ensure that this script completes fully (no interruptions) before continuing on. User can use the ``--skip`` or ``-s`` flag to skip steps:
@@ -96,7 +92,7 @@ Run the following script based off which compiler you would like to use.
.. code-block:: shell
./build-setup.sh riscv-tools # or esp-tools
./build-setup.sh riscv-tools
This script wraps around the conda environment initialization process, initializes all submodules (with the ``init-submodules-no-riscv-tools.sh`` script), installs a toolchain, and runs other setups.
See ``./build-setup.sh --help`` for more details on what this does and how to disable parts of the setup.
@@ -107,7 +103,7 @@ See ``./build-setup.sh --help`` for more details on what this does and how to di
.. Note:: If you already have a working conda environment setup, separate Chipyard clones can use that pre-used environment in combination with running the aforementioned scripts yourself (``init-submodules...``, ``build-toolchain...``, etc).
.. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock and https://github.com/ucb-bar/esp-tools-feedstock repositories (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself.
.. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock repository (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself.
By running the following command you should see a environment listed with the path ``$CHIPYARD_DIRECTORY/.conda-env``.

4
docs/Customization/Custom-Chisel.rst
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@@ -59,8 +59,8 @@ should look something like this:
.. code-block:: scala
lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
sha3, dsptools, `rocket-dsp-utils`,
.dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
yourproject, // <- added to the middle of the list for simplicity
constellation, mempress)

106
docs/Customization/Firrtl-Transforms.rst
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@@ -1,106 +0,0 @@
.. _firrtl-transforms:
Adding a Firrtl Transform
=========================
Similar to how LLVM IR passes can perform transformations and optimizations on software, FIRRTL transforms can
modify Chisel-elaborated RTL.
As mentioned in Section :ref:`Tools/FIRRTL:firrtl`, transforms are modifications that happen on the FIRRTL IR that can modify a circuit.
Transforms are a powerful tool to take in the FIRRTL IR that is emitted from Chisel and run analysis or convert the circuit into a new form.
The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler
------------------------------------------------------
In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler (SFC) and the MLIR FIRRTL compiler (MFC).
They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster (the generated Verilog will be different). In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will
compile CHIRRTL into Verilog (as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value,
we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied.
For more information on MLIR FIRRTL Compiler, please visit https://mlir.llvm.org/ and https://circt.llvm.org/.
Where to add transforms
-----------------------
In Chipyard, the FIRRTL compiler is called multiple times to create a "Top" file that contains the DUT and a "Model" file containing the test harness, which instantiates the DUT.
The "Model" file does not contain the DUT's module definition or any of its submodules.
This is done by the ``tapeout`` SBT project (located in ``tools/barstools/tapeout``) which calls ``GenerateModelStageMain`` (a function that wraps the multiple FIRRTL compiler calls and extra transforms).
.. literalinclude:: ../../common.mk
:language: make
:start-after: DOC include start: FirrtlCompiler
:end-before: DOC include end: FirrtlCompiler
If you look inside of the `tools/barstools/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala <https://github.com/ucb-bar/barstools/blob/master/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala>`__ file,
you can see that FIRRTL is invoked for "Model". Currently, the FIRRTL compiler is agnostic to the ``TOP`` and ``MODEL`` differentiation,
and the user is responsible for providing annotations that will inform the compiler where(``TOP`` vs ``MODEL``) to perform the custom FIRRTL transformations.
For more information on Barstools, please visit the :ref:`Tools/Barstools:Barstools` section.
Examples of transforms
----------------------
There are multiple examples of transforms that you can apply and are spread across the FIRRTL ecosystem.
Within FIRRTL there is a default set of supported transforms located in https://github.com/freechipsproject/firrtl/tree/master/src/main/scala/firrtl/transforms.
This includes transforms that can flatten modules (``Flatten``), group modules together (``GroupAndDedup``), and more.
Transforms can be standalone or can take annotations as input. Annotations are used to pass information between FIRRTL transforms. This includes information on
what modules to flatten, group, and more. Annotations can be added to the code by
adding them to your Chisel source or by creating a serialized annotation ``json`` file and adding it to the FIRRTL compiler
(note: annotating the Chisel source will automatically serialize the annotation as a ``json`` snippet into the build system for you).
**The recommended way to annotate something is to do it in the Chisel source, but not all annotation types have Chisel APIs**.
The example below shows two ways to annotate the signal using the ``DontTouchAnnotation``
(makes sure that a particular signal is not removed by the "Dead Code Elimination" pass in FIRRTL):
* use the Chisel API/wrapper function called ``dontTouch`` that does this automatically for you (more `dontTouch <https://www.chisel-lang.org/api/SNAPSHOT/chisel3/dontTouch$.html>`__ information):
* directly annotate the signal with the ``annotate`` function and the ``DontTouchAnnotation`` class if there is no Chisel API for it (note: most FIRRTL annotations have Chisel APIs for them)
.. code-block:: scala
class TopModule extends Module {
...
val submod = Module(new Submodule)
...
}
class Submodule extends Module {
...
val some_signal := ...
// MAIN WAY TO USE `dontTouch`
// how to annotate if there is a Chisel API/wrapper
chisel3.dontTouch(some_signal)
// how to annotate WITHOUT a Chisel API/wrapper
annotate(new ChiselAnnotation {
def toFirrtl = DontTouchAnnotation(some_signal.toNamed)
})
...
}
Here is an example of the ``DontTouchAnnotation`` when it is serialized:
.. code-block:: json
[
{
"class": "firrtl.transforms.DontTouchAnnotation",
"target": "~TopModule|Submodule>some_signal"
}
]
In this case, the specific syntax depends on the type of annotation and its fields.
One of the easier ways to figure out the serialized syntax is to first try and find a Chisel
annotation to add to the code. Then you can look at the collateral that is generated from the
build system, find the ``*.anno.json``, and find the proper syntax for the annotation.
Once ``yourAnnoFile.json`` is created then you can add ``-faf yourAnnoFile.json`` to the FIRRTL
compiler invocation in ``common.mk``.
.. literalinclude:: ../../common.mk
:language: make
:start-after: DOC include start: FirrtlCompiler
:end-before: DOC include end: FirrtlCompiler
If you are interested in writing FIRRTL transforms please refer to the FIRRTL documentation located here:
https://github.com/freechipsproject/firrtl/wiki.

36
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@@ -4,7 +4,7 @@ Heterogeneous SoCs
===============================
The Chipyard framework involves multiple cores and accelerators that can be composed in arbitrary ways.
This discussion will focus on how you combine Rocket, BOOM and Hwacha in particular ways to create a unique SoC.
This discussion will focus on how you combine Rocket and BOOM in particular ways to create a unique SoC.
Creating a Rocket and BOOM System
-------------------------------------------
@@ -21,40 +21,6 @@ The following example shows a dual core BOOM with a single core Rocket.
:end-before: DOC include end: DualBoomAndSingleRocket
Adding Hwachas
-------------------------------------------
Adding a Hwacha accelerator is as easy as adding the ``DefaultHwachaConfig`` so that it can setup the Hwacha parameters and add itself to the ``BuildRoCC`` parameter.
An example of adding a Hwacha to all tiles in the system is below.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala
:language: scala
:start-after: DOC include start: BoomAndRocketWithHwacha
:end-before: DOC include end: BoomAndRocketWithHwacha
In this example, Hwachas are added to both BOOM tiles and to the Rocket tile.
All with the same Hwacha parameters.
Assigning Accelerators to Specific Tiles with MultiRoCC
-------------------------------------------------------
Located in ``generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala`` is a config fragment that provides support for adding RoCC accelerators to specific tiles in your SoC.
Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile.
For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles.
An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala
:language: scala
:start-after: DOC include start: DualBoomAndRocketOneHwacha
:end-before: DOC include end: DualBoomAndRocketOneHwacha
The ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``0`` corresponds to the Rocket core).
Finally, the ``WithMultiRoCC`` config fragment is called.
This config fragment sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default.
This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter.
If this is used earlier in the configuration sequence, then MultiRoCC does not work.
This config fragment can be changed to put more accelerators on more cores by changing the arguments to cover more ``hartId``'s (i.e. ``WithMultiRoCCHwacha(0,1,3,6,...)``).
Since config fragments are applied from right-to-left (or bottom-to-top as they are formatted here), the right-most config fragment specifying a core (which is ``freechips.rocketchip.subsystem.WithNBigCores`` in the example above) gets the first hart ID.
Consider this config:

13
docs/Customization/Incorporating-Verilog-Blocks.rst
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@@ -33,19 +33,6 @@ different directory from Chisel (Scala) sources.
vsrc/
YourFile.v
In addition to the steps outlined in the previous section on adding a
project to the ``build.sbt`` at the top level, it is also necessary to
add any projects that contain Verilog IP as dependencies to the
``tapeout`` project. This ensures that the Verilog sources are visible
to the downstream FIRRTL passes that provide utilities for integrating
Verilog files into the build process, which are part of the
``tapeout`` package in ``barstools/tapeout``.
.. code-block:: scala
lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
.dependsOn(chisel_testers, example, yourproject)
.settings(commonSettings)
For this concrete GCD example, we will be using a ``GCDMMIOBlackBox``
Verilog module that is defined in the ``chipyard`` project. The Scala

3
docs/Customization/index.rst
View File

@@ -29,8 +29,6 @@ We also provide information on:
- The boot process for Chipyard SoCs
- Examples of FIRRTL transforms used in Chipyard, and where they are specified
We recommend reading all these pages in order. Hit next to get started!
.. toctree::
@@ -50,5 +48,4 @@ We recommend reading all these pages in order. Hit next to get started!
Incorporating-Verilog-Blocks
Memory-Hierarchy
Boot-Process
Firrtl-Transforms
IOBinders

15
docs/Generators/Hwacha.rst
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@@ -1,15 +0,0 @@
Hwacha
====================================
The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption.
The Hwacha project is inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures such as Scale and Maven
The Hwacha project includes the Hwacha microarchitecture generator, as well as the ``XHwacha`` non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal.
For more information on the Hwacha project, please visit the `Hwacha website <https://bar.eecs.berkeley.edu/projects/hwacha.html>`__ or search for "Krste Asanovic Hwacha" on Google Scholar for publications.
To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config fragment to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache).
To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under `generators/hwacha/src/main/scala/configs.scala <https://github.com/ucb-bar/hwacha/blob/master/src/main/scala/configs.scala>`__ to see the possible configuration parameters.
Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and assemble its vector instructions.
To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it.

81
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@@ -1,81 +0,0 @@
SHA3 RoCC Accelerator
===================================
The SHA3 accelerator is a basic RoCC accelerator for the SHA3 hashing algorithm.
We like using SHA3 in Chipyard tutorial content because it is a self-contained, simple
example of integrating a custom accelerator into Chipyard.
Introduction
-----------------------------------
Secure hashing algorithms represent a class of hashing functions that provide four attributes: ease
of hash computation, inability to generate the message from the hash (one-way property), inability
to change the message and not the hash (weakly collision free property), and inability to find
two messages with the same hash (strongly collision free property). The National Institute of
Standards and Technology (NIST) recently held a competition for a new algorithm to be added to
its set of Secure Hashing Algorithms (SHA). In 2012 the winner was determined to be the Keccak
hashing function and a rough specification for SHA3 was established. The algorithm operates on
variable length messages with a sponge function, and thus alternates between absorbing chunks of
the message into a set of state bits and permuting the state. The absorbing is a simple bitwise
XOR while the permutation is a more complex function composed of several operations, χ, θ, ρ,
π, ι, that all perform various bitwise operations, including rotations, parity calculations, XORs,
etc. The Keccak hashing function is parameterized for different sizes of state and message chunks
but for this accelerator we will only support the Keccak-256 variant with 1600 bits of state and
1088 bit message chunks. A diagram of the SHA3 accelerator is shown below.
.. image:: ../_static/images/sha3.png
Technical Details
------------------------------------
The accelerator is designed around three sub-systems, an
interface with the processor, an interface with memory, and
the actual hashing computation system. The interface
with the processor is designed using the ROCC interface for
coprocessors integrating with the RISC-V Rocket/BOOM
processor. It includes the ability to transfer two 64 bit
words to the co-processor, the request for a return value,
and a small field for the function requested. The accelerator
receives these requests using a ready/valid interface. The
ROCC instruction is parsed and the needed information is
stored into a execution context. The execution context contains
the memory address of the message being hashed, the memory address
to store the resulting hash in, the length of the message, and
several other control fields.
Once the execution context is valid the memory subsystem
then begins to fetch chunks of the message. The memory
subsystem is fully decoupled from the other subsystems
and maintains a single full round memory buffers.
The accelerators memory interface can provide a
maximum of one 64 bit word per cycle which corresponds
to 17 requests needed to fill a buffer (the size is dictated by
the SHA3 algorithm). Memory requests to fill these buffers
are sent out as rapidly as the memory interface can handle,
with a tag field set to allow the different memory buffers
requests to be distinguished, as they may be returned out of
order. Once the memory subsystem has filled a buffer the
control unit absorbs the buffer into the execution
context, at which point the execution context is free to
begin permutation, and the memory buffer is free to send
more memory requests.
After the buffer is absorbed, the hashing computation
subsystem begins the permutation operations. Once
the message is fully hashed, the hash is written to memory
with a simple state machine.
Using a SHA3 Accelerator
------------------------
Since the SHA3 accelerator is designed as a RoCC accelerator,
it can be mixed into a Rocket or BOOM core by overriding the
``BuildRoCC`` key. The config fragment is defined in the SHA3
generator. An example configuration highlighting the use of
this config fragment is shown here:
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
:language: scala
:start-after: DOC include start: Sha3Rocket
:end-before: DOC include end: Sha3Rocket
The SHA3 example baremetal and Linux tests are located in the SHA3 repository.
Please refer to its `README.md <https://github.com/ucb-bar/sha3/blob/master/README.md>`_ for more information on how to run/build the tests.

2
docs/Generators/index.rst
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@@ -22,12 +22,10 @@ so changes to the generators themselves will automatically be used when building
Rocket
BOOM
Constellation
Hwacha
Gemmini
IceNet
TestChipIP
Rocket-Chip-Generators
SHA3
CVA6
Ibex
fft

13
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@@ -50,16 +50,16 @@ This will elaborate the ``RocketConfig`` in the example project.
.. Note:: The elaboration of ``RocketConfig`` requires about 6.5 GB of main memory. Otherwise the process will fail with ``make: *** [firrtl_temp] Error 137`` which is most likely related to limited resources. Other configurations might require even more main memory.
An executable called ``simulator-chipyard-RocketConfig`` will be produced.
An executable called ``simulator-chipyard.harness-RocketConfig`` will be produced.
This executable is a simulator that has been compiled based on the design that was built.
You can then use this executable to run any compatible RV64 code.
For instance, to run one of the riscv-tools assembly tests.
.. code-block:: shell
./simulator-chipyard-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
./simulator-chipyard.harness-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
.. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``.
.. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard.harness-RocketConfig`` instead of ``simulator-chipyard.harness-RocketConfig``.
The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file.
@@ -155,13 +155,6 @@ Therefore, in order to simulate a simple Rocket-based example system we can use:
./simulator-<yourproject>-<yourconfig> ...
All ``make`` targets that can be applied to the default example, can also be applied to custom project using the custom environment variables. For example, the following code example will run the RISC-V assembly benchmark suite on the Hwacha subproject:
.. code-block:: shell
make SUB_PROJECT=hwacha run-asm-tests
Finally, in the ``generated-src/<...>-<package>-<config>/`` directory resides all of the collateral while the generated Verilog source files resides in ``generated-src/<...>-<package>-<config>/gen-collateral`` for the build/simulation.
Specifically, for ``CONFIG=RocketConfig`` the SoC top-level (``TOP``) Verilog file is ``ChipTop.sv`` while the (``Model``) file is ``TestHarness.sv``.

2
docs/Tools/FIRRTL.rst
View File

@@ -7,6 +7,4 @@ Without going into too much detail, FIRRTL is consumed by FIRRTL compilers which
An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
Once the transformations are done, a Verilog file is emitted and the build process is done.
To see how FIRRTL is transformed to Verilog in Chipyard, please visit the :ref:`firrtl-transforms` section.
For more information on FIRRTL, please visit their `website <https://chisel-lang.org/firrtl/>`__.

14
docs/Tools/Barstools.rst → docs/Tools/Tapeout-Tools.rst
View File

@@ -1,7 +1,7 @@
Barstools
Tapeout-Tools
===============================
Barstools is a collection of useful FIRRTL transformations and compilers to help the build process.
Tapeout-Tools is a collection of useful FIRRTL transformations and compilers to help the build process.
Included in the tools are a MacroCompiler (used to map Chisel memory constructs to vendor SRAMs), FIRRTL transforms (to separate harness and top-level SoC files), and more.
Mapping technology SRAMs (MacroCompiler)
@@ -23,16 +23,16 @@ An external module reference is a FIRRTL construct that enables a design to refe
A list of unique SRAM configurations is output to a ``.conf`` file by FIRRTL, which is used to map technology SRAMs.
Without this transform, FIRRTL will map all ``SeqMem`` s to flip-flop arrays with equivalent behavior, which may lead to a design that is difficult to route.
The ``.conf`` file is consumed by a tool called MacroCompiler, which is part of the :ref:`Tools/Barstools:Barstools` scala package.
The ``.conf`` file is consumed by a tool called MacroCompiler, which is part of the :ref:`Tools/Tapeout-Tools:Tapeout-Tools` scala package.
MacroCompiler is also passed an ``.mdf`` file that describes the available list of technology SRAMs or the capabilities of the SRAM compiler, if one is provided by the foundry.
Typically a foundry SRAM compiler will be able to generate a set of different SRAMs collateral based on some requirements on size, aspect ratio, etc. (see :ref:`Tools/Barstools:SRAM MDF Fields`).
Typically a foundry SRAM compiler will be able to generate a set of different SRAMs collateral based on some requirements on size, aspect ratio, etc. (see :ref:`Tools/Tapeout-Tools:SRAM MDF Fields`).
Using a user-customizable cost function, MacroCompiler will select the SRAMs that are the best fit for each dimensionality in the ``.conf`` file.
This may include over provisioning (e.g. using a 64x1024 SRAM for a requested 60x1024, if the latter is not available) or arraying.
Arraying can be done in both width and depth, as well as to solve masking constraints.
For example, a 128x2048 array could be composed of four 64x1024 arrays, with two macros in parallel to create two 128x1024 virtual SRAMs which are combinationally muxed to add depth.
If this macro requires byte-granularity write masking, but no technology SRAMs support masking, then the tool may choose to use thirty-two 8x1024 arrays in a similar configuration.
You may wish to create a cache of your available SRAM macros either manually, or via a script. A reference script for creating a JSON of your SRAM macros is in the `asap7 technology library folder <https://github.com/ucb-bar/hammer/blob/8fd1486499b875d56f09b060f03a62775f0a6aa7/src/hammer-vlsi/technology/asap7/sram-cache-gen.py>`__.
For information on writing ``.mdf`` files, look at `MDF on github <https://github.com/ucb-bar/plsi-mdf>`__ and a brief description in :ref:`Tools/Barstools:SRAM MDF Fields` section.
For information on writing ``.mdf`` files, look at `MDF on github <https://github.com/ucb-bar/plsi-mdf>`__ and a brief description in :ref:`Tools/Tapeout-Tools:SRAM MDF Fields` section.
The output of MacroCompiler is a Verilog file containing modules that wrap the technology SRAMs into the specified interface names from the ``.conf``.
If the technology supports an SRAM compiler, then MacroCompiler will also emit HammerIR that can be passed to Hammer to run the compiler itself and generate design collateral.
@@ -105,7 +105,7 @@ This is necessary to facilitate post-synthesis and post-place-and-route simulati
Simulations, after your design goes through a VLSI flow, will use the verilog netlist generated from the flow and will need an untouched test harness to drive it.
Separating these components into separate files makes this straightforward.
Without the separation the file that included the test harness would also redefine the DUT which is often disallowed in simulation tools.
To do this, there is a FIRRTL ``App`` in :ref:`Tools/Barstools:Barstools` called ``GenerateTopAndHarness``, which runs the appropriate transforms to elaborate the modules separately.
To do this, there is a FIRRTL ``App`` in :ref:`Tools/Tapeout-Tools:Tapeout-Tools` called ``GenerateTopAndHarness``, which runs the appropriate transforms to elaborate the modules separately.
This also renames modules in the test harness so that any modules that are instantiated in both the test harness and the chip are uniquified.
.. Note:: For VLSI projects, this ``App`` is run instead of the normal FIRRTL ``App`` to elaborate Verilog.
@@ -133,5 +133,5 @@ This, unfortunately, breaks the process-agnostic RTL abstraction, so it is recom
The simplest way to do this is to have a config fragment that when included updates instantiates the IO cells and connects them in the test harness.
When simulating chip-specific designs, it is important to include the IO cells.
The IO cell behavioral models will often assert if they are connected incorrectly, which is a useful runtime check.
They also keep the IO interface at the chip and test harness boundary (see :ref:`Tools/Barstools:Separating the Top module from the TestHarness module`) consistent after synthesis and place-and-route,
They also keep the IO interface at the chip and test harness boundary (see :ref:`Tools/Tapeout-Tools:Separating the Top module from the TestHarness module`) consistent after synthesis and place-and-route,
which allows the RTL simulation test harness to be reused.

2
docs/Tools/index.rst
View File

@@ -12,4 +12,4 @@ The following pages will introduce them, and how we can use them in order to gen
FIRRTL
Treadle
Dsptools
Barstools
Tapeout-Tools

4
docs/VLSI/Basic-Flow.rst
View File

@@ -56,7 +56,7 @@ We will do so by calling ``make buildfile`` with appropriate Chipyard configurat
As in the rest of the Chipyard flows, we specify our SoC configuration using the ``CONFIG`` make variable.
However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module.
Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on.
The makefile will automatically call tools such as Barstools and the MacroCompiler (:ref:`Tools/Barstools:barstools`) in order to make the generated Verilog more VLSI friendly.
The makefile will automatically call tools such as Tapeout-Tools and the MacroCompiler (:ref:`Tools/Tapeout-Tools:Tapeout-Tools`) in order to make the generated Verilog more VLSI friendly.
By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``TOP_MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``TOP_MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints).
We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``.
@@ -227,7 +227,7 @@ While hierarchical physical design can be performed in multiple ways (top-down,
The bottom-up approach traverses a tree representing the hierarchy starting from the leaves and towards the direction of the root (the "top level"), and runs the physical design flow on each node of the hierarchy tree using the previously layed-out children nodes.
As nodes get closer to the root (or "top level") of the hierarchy, largers sections of the design get layed-out.
The Hammer hierarchical flow relies on a manually-specified descrition of the desired heirarchy tree. The specification of the heirarchy tree is defined based on the instance names in the generated Verilog, which sometime make this specification challenging due to inconsisent instance names. Additionally, the specification of the heirarchy tree is intertwined with the manual specification of a floorplan for the design.
The Hammer hierarchical flow relies on a manually-specified description of the desired hierarchy tree. The specification of the hierarchy tree is defined based on the instance names in the generated Verilog, which sometime make this specification challenging due to inconsisent instance names. Additionally, the specification of the hierarchy tree is intertwined with the manual specification of a floorplan for the design.
For example, if we choose to specifiy the previously mentioned ``GemminiRocketConfig`` configuration in a hierarchical fashion in which the Gemmini accelerator and the last-level cache are run separetly from the top-level SoC, we would replace the floorplan example in ``example-design.yml`` from the :ref:`VLSI/Basic-Flow:Place-and-Route` section with the following specification:

2
docs/VLSI/Building-A-Chip.rst
View File

@@ -10,7 +10,7 @@ Transforming the RTL
--------------------
Building a chip requires specializing the generic verilog emitted by FIRRTL to adhere to the constraints imposed by the technology used for fabrication.
This includes mapping Chisel memories to available technology macros such as SRAMs, mapping the input and output of your chip to connect to technology IO cells, see :ref:`Tools/Barstools:Barstools`.
This includes mapping Chisel memories to available technology macros such as SRAMs, mapping the input and output of your chip to connect to technology IO cells, see :ref:`Tools/Tapeout-Tools:Tapeout-tools`.
In addition to these required transformations, it may also be beneficial to transform the RTL to make it more amenable to hierarchical physical design easier.
This often includes modifying the logical hierarchy to match the physical hierarchy through grouping components together or flattening components into a single larger module.

2
fpga/Makefile
View File

@@ -87,6 +87,8 @@ ifeq ($(SUB_PROJECT),arty100t)
FPGA_BRAND ?= xilinx
endif
export USE_CHISEL6=1
include $(base_dir)/variables.mk
# default variables to build the arty example

2
fpga/fpga-shells

Submodule fpga/fpga-shells updated: 6019bb3508...474ad19113

2
fpga/src/main/scala/arty/Configs.scala
View File

@@ -5,7 +5,6 @@ import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
import freechips.rocketchip.system._
import freechips.rocketchip.tile._
@@ -25,7 +24,6 @@ class WithArtyTweaks extends Config(
new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.config.WithDTSTimebase(32000) ++
new chipyard.config.WithSystemBusFrequency(32) ++
new chipyard.config.WithFrontBusFrequency(32) ++
new chipyard.config.WithControlBusFrequency(32) ++

1
fpga/src/main/scala/arty/IOBinders.scala
View File

@@ -1,7 +1,6 @@
package chipyard.fpga.arty
import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug}

1
fpga/src/main/scala/vc707/TestHarness.scala
View File

@@ -1,6 +1,5 @@
package chipyard.fpga.vc707
import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
import org.chipsalliance.cde.config.{Parameters}

1
fpga/src/main/scala/vcu118/TestHarness.scala
View File

@@ -1,7 +1,6 @@
package chipyard.fpga.vcu118
import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
import org.chipsalliance.cde.config.{Parameters}

2
generators/bar-fetchers

Submodule generators/bar-fetchers updated: 45380026ff...bd02692fe6

11
generators/chipyard/src/main/resources/vsrc/Analog.v Normal file
View File

@@ -0,0 +1,11 @@
// See LICENSE for license details
`timescale 1ns/1ps
module AnalogConst #(CONST, WIDTH) (
output [WIDTH-1:0] io
);
assign io = CONST;
endmodule

2
generators/chipyard/src/main/scala/ChipTop.scala
View File

@@ -10,7 +10,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleI
import freechips.rocketchip.util.{DontTouch}
import chipyard.iobinders._
import barstools.iocell.chisel._
import chipyard.iocell._
case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p))

5
generators/chipyard/src/main/scala/System.scala
View File

@@ -80,9 +80,10 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
}
}).toList.flatten)
// disable inwards monitors from node since the class with this trait (i.e. DigitalTop)
// doesn't provide an implicit clock to those monitors
mbus.coupleTo(s"memory_controller_port_named_$portName") {
(memTLNode
:*= TLBuffer()
(DisableMonitors { implicit p => memTLNode :*= TLBuffer() }
:*= TLSourceShrinker(1 << idBits)
:*= TLWidthWidget(mbus.beatBytes)
:*= _)

2
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
View File

@@ -7,7 +7,7 @@ import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import barstools.iocell.chisel._
import chipyard.iocell._
// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate
// the requested clocks. This also adds TileLink ClockDivider and ClockSelector

30
generators/chipyard/src/main/scala/config/HeteroConfigs.scala
View File

@@ -12,36 +12,6 @@ class LargeBoomAndRocketConfig extends Config(
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include start: BoomAndRocketWithHwacha
class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
new boom.v3.common.WithNLargeBooms(1) ++ // add 1 boom core
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include end: BoomAndRocketWithHwacha
class LargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc
new chipyard.config.WithMultiRoCCHwacha(0) ++ // put hwacha on hart-0 (rocket)
new hwacha.DefaultHwachaConfig ++ // set default hwacha config keys
new boom.v3.common.WithNLargeBooms(1) ++ // add 1 boom core
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include start: DualBoomAndRocketOneHwacha
class DualLargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc
new chipyard.config.WithMultiRoCCHwacha(0) ++ // put hwacha on hart-0 (rocket)
new hwacha.DefaultHwachaConfig ++ // set default hwacha config keys
new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include end: DualBoomAndRocketOneHwacha
class DualLargeBoomAndDualRocketConfig extends Config(
new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores
new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // add 2 rocket cores

6
generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
View File

@@ -17,3 +17,9 @@ class NoCoresConfig extends Config(
new chipyard.config.WithNoDebug ++
new chipyard.config.WithNoPLIC ++
new chipyard.config.AbstractConfig)
// A config that uses a empty chiptop module with no rocket-chip soc components
class EmptyChipTopConfig extends Config(
new chipyard.example.WithEmptyChipTop ++
new chipyard.config.AbstractConfig // since we aren't using rocket-chip, this doesn't do anything
)

14
generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
View File

@@ -33,13 +33,6 @@ class LeanGemminiPrintfRocketConfig extends Config(
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class HwachaRocketConfig extends Config(
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MempressRocketConfig extends Config(
new mempress.WithMemPress ++ // use Mempress (memory traffic generation) accelerator
new chipyard.config.WithExtMemIdBits(7) ++ // use 7 bits for tl like request id
@@ -50,13 +43,6 @@ class MempressRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class HwachaLargeBoomV3Config extends Config(
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
new boom.v3.common.WithNLargeBooms(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class AES256ECBRocketConfig extends Config(
new aes.WithAES256ECBAccel ++ // use Caliptra AES 256 ECB accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++

22
generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
View File

@@ -1,22 +0,0 @@
package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// --------------
// Rocket+SHA3 Configs
// These live in a separate file to simplify patching out for the tutorials.
// --------------
// DOC include start: Sha3Rocket
class Sha3RocketConfig extends Config(
new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: Sha3Rocket
class Sha3RocketPrintfConfig extends Config(
new sha3.WithSha3Printf ++
new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

24
generators/chipyard/src/main/scala/config/TutorialConfigs.scala
View File

@@ -12,10 +12,6 @@ import scala.collection.immutable.ListMap
// For each of 4 phases, participants will customize and build a
// small demonstration config.
// This file is designed to be used after running chipyard/scripts/tutorial-setup.sh,
// which removes the SHA3 accelerator RTL, and provides participants
// the experience of integrating external RTL.
// This file was originally developed for the cancelled ASPLOS-2020
// Chipyard tutorial. While the configs here work, the corresponding
// slideware has not yet been created.
@@ -54,26 +50,6 @@ class TutorialMMIOConfig extends Config(
new chipyard.config.AbstractConfig
)
// Tutorial Phase 3: Integrate a SHA3 RoCC accelerator
class TutorialSha3Config extends Config(
// Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo
// new sha3.WithSha3Accel ++
// For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig
)
// Tutorial Phase 4: Integrate a Black-box verilog version of the SHA3 RoCC accelerator
class TutorialSha3BlackBoxConfig extends Config(
// Uncomment these lines once SHA3 is integrated
// new sha3.WithSha3BlackBox ++ // Specify we want the Black-box verilog version of Sha3 Ctrl
// new sha3.WithSha3Accel ++
// For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig
)
// Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators
class TutorialNoCConfig extends Config(

9
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
View File

@@ -89,9 +89,12 @@ class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site,
* Mixins to set the dtsFrequency field of BusParams -- these will percolate its way
* up the diplomatic graph to the clock sources.
*/
class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
})
class WithPeripheryBusFrequency(freqMHz: Double) extends Config(
new freechips.rocketchip.subsystem.WithTimebase((freqMHz * 1e3).toLong) ++ // Match DTS timebase to PBUS (i.e. RTC) frequency. Makes RTC 'tick' at the PBUS rate.
new Config((site, here, up) => {
case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
})
)
class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
})

42
generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
View File

@@ -6,7 +6,6 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.tile._
import freechips.rocketchip.diplomacy._
import hwacha.{Hwacha}
import gemmini._
import chipyard.{TestSuitesKey, TestSuiteHelper}
@@ -34,47 +33,6 @@ class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) =>
}
})
/**
* Config fragment to add Hwachas to cores based on hart
*
* For ex:
* Core 0, 1, 2, 3 have been defined earlier
* with tileIds of 0, 1, 2, 3 respectively
* And you call WithMultiRoCCHwacha(0,1)
* Then Core 0 and 1 will get a Hwacha
*
* @param harts harts to specify which will get a Hwacha
*/
class WithMultiRoCCHwacha(harts: Int*) extends Config(
new chipyard.config.WithHwachaTest ++
new Config((site, here, up) => {
case MultiRoCCKey => {
up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
(i -> Seq((p: Parameters) => {
val hwacha = LazyModule(new Hwacha()(p))
hwacha
}))
}
}
})
)
class WithHwachaTest extends Config((site, here, up) => {
case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
up(TestSuitesKey).apply(tileParams, suiteHelper, p)
import hwacha.HwachaTestSuites._
suiteHelper.addSuites(rv64uv.map(_("p")))
suiteHelper.addSuites(rv64uv.map(_("vp")))
suiteHelper.addSuite(rv64sv("p"))
suiteHelper.addSuite(hwachaBmarks)
"SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha"
}
})
/**
* The MultiRoCCGemmini fragment functions similarly to the
* WithMultiRoCCHwacha fragment defined above
*/
class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data](
harts: Int*)(gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig) extends Config((site, here, up) => {
case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i =>

4
generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
View File

@@ -18,10 +18,6 @@ class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8)
})
class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => {
case DTSTimebase => freqMHz
})
// Adds buffers on the interior of the inclusive LLC, to improve PD
class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)

5
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -131,3 +131,8 @@ class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams]
class WithSV48IfPossible extends Config((site, here, up) => {
case PgLevels => if (site(XLen) == 64) 4 /* Sv48 */ else up(PgLevels)
})
// Uses SV39 if possible, otherwise default to the Rocket Chip core default
class WithSV39 extends Config((site, here, up) => {
case PgLevels => { require(site(XLen) == 64); 3; }
})

2
generators/chipyard/src/main/scala/example/CustomChipTop.scala
View File

@@ -6,7 +6,7 @@ import chipyard.iobinders._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy.{InModuleBody}
import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations}
import barstools.iocell.chisel._
import chipyard.iocell._
import chipyard._
import chipyard.harness.{BuildTop}
import sifive.blocks.devices.uart._

21
generators/chipyard/src/main/scala/example/EmptyChipTop.scala Normal file
View File

@@ -0,0 +1,21 @@
package chipyard.example
import chisel3._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util.{DontTouch}
import chipyard._
import chipyard.harness.{BuildTop}
class EmptyChipTop(implicit p: Parameters) extends LazyModule {
override lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) with DontTouch {
// Your custom non-rocketchip-soc stuff here
}
}
class WithEmptyChipTop extends Config((site, here, up) => {
case BuildTop => (p: Parameters) => new EmptyChipTop()(p)
})

2
generators/chipyard/src/main/scala/example/FlatChipTop.scala
View File

@@ -13,7 +13,7 @@ import chipyard.{BuildSystem, DigitalTop}
import chipyard.harness.{BuildTop}
import chipyard.clocking._
import chipyard.iobinders._
import barstools.iocell.chisel._
import chipyard.iocell._
import testchipip.serdes.{SerialTLKey}
class WithFlatChipTop extends Config((site, here, up) => {

2
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
View File

@@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem._
import freechips.rocketchip.util._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.devices.debug.{SimJTAG}
import barstools.iocell.chisel._
import chipyard.iocell._
import testchipip.dram.{SimDRAM}
import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO}
import testchipip.soc.{TestchipSimDTM}

1
generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
View File

@@ -99,6 +99,7 @@ trait HasHarnessInstantiators {
if (p(DontTouchChipTopPorts)) {
duts.map(_ match {
case d: DontTouch => d.dontTouchPorts()
case _ =>
})
}

13
generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
View File

@@ -30,30 +30,29 @@ object ApplyMultiHarnessBinders {
}
}
class MultiHarnessBinder[T <: Port[_], S <: HasHarnessInstantiators](
class MultiHarnessBinder[T <: Port[_], U <: Port[_], S <: HasHarnessInstantiators](
chip0: Int, chip1: Int,
chip0portFn: T => Boolean, chip1portFn: T => Boolean,
connectFn: (S, T, T) => Unit
)(implicit tag0: ClassTag[T], tag1: ClassTag[S]) extends Config((site, here, up) => {
chip0portFn: T => Boolean, chip1portFn: U => Boolean,
connectFn: (S, T, U) => Unit
)(implicit tag0: ClassTag[T], tag1: ClassTag[U], tag2: ClassTag[S]) extends Config((site, here, up) => {
// Override any HarnessBinders for chip0/chip1
case MultiChipParameters(`chip0`) => new Config(
new HarnessBinder({case (th: S, port: T, chipId: Int) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0))
)
case MultiChipParameters(`chip1`) => new Config(
new HarnessBinder({case (th: S, port: T, chipId: Int) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1))
new HarnessBinder({case (th: S, port: U, chipId: Int) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1))
)
// Set the multiharnessbinder key
case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) :+ {
((th: S, chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => {
val chip0Port: Seq[T] = chip0Ports.collect { case (p: T) if chip0portFn(p) => p }
val chip1Port: Seq[T] = chip1Ports.collect { case (p: T) if chip1portFn(p) => p }
val chip1Port: Seq[U] = chip1Ports.collect { case (p: U) if chip1portFn(p) => p }
require(chip0Port.size == 1 && chip1Port.size == 1)
connectFn(th, chip0Port(0), chip1Port(0))
})
}
})
class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder(
chip0, chip1,
(p0: SerialTLPort) => p0.portId == chip0portId,

2
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
View File

@@ -27,7 +27,7 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import tracegen.{TraceGenSystemModuleImp}
import barstools.iocell.chisel._
import chipyard.iocell._
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.spi.{SPIChipIO}

18
generators/chipyard/src/main/scala/iocell/Analog.scala Normal file
View File

@@ -0,0 +1,18 @@
// See LICENSE for license details
package chipyard.iocell
import chisel3._
import chisel3.util.{HasBlackBoxResource}
import chisel3.experimental.{Analog, IntParam}
class AnalogConst(value: Int, width: Int = 1)
extends BlackBox(Map("CONST" -> IntParam(value), "WIDTH" -> IntParam(width)))
with HasBlackBoxResource {
val io = IO(new Bundle { val io = Analog(width.W) })
addResource("/vsrc/Analog.v")
}
object AnalogConst {
def apply(value: Int, width: Int = 1) = Module(new AnalogConst(value, width)).io.io
}

338
generators/chipyard/src/main/scala/iocell/IOCell.scala Normal file
View File

@@ -0,0 +1,338 @@
// See LICENSE for license details
package chipyard.iocell
import chisel3._
import chisel3.util.{Cat, HasBlackBoxInline}
import chisel3.reflect.DataMirror
import chisel3.experimental.{Analog, BaseModule}
// The following four IO cell bundle types are bare-minimum functional connections
// for modeling 4 different IO cell scenarios. The intention is that the user
// would create wrapper modules that extend these interfaces with additional
// control signals. These are loosely similar to the sifive-blocks PinCtrl bundles
// (https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/pinctrl/PinCtrl.scala),
// but we want to avoid a dependency on an external libraries.
/** The base IO bundle for an analog signal (typically something with no digital buffers inside)
* pad: off-chip (external) connection
* core: internal connection
*/
class AnalogIOCellBundle extends Bundle {
val pad = Analog(1.W) // Pad/bump signal (off-chip)
val core = Analog(1.W) // core signal (on-chip)
}
/** The base IO bundle for a signal with runtime-controllable direction
* pad: off-chip (external) connection
* i: input to chip logic (output from IO cell)
* ie: enable signal for i
* o: output from chip logic (input to IO cell)
* oe: enable signal for o
*/
class DigitalGPIOCellBundle extends Bundle {
val pad = Analog(1.W)
val i = Output(Bool())
val ie = Input(Bool())
val o = Input(Bool())
val oe = Input(Bool())
}
/** The base IO bundle for a digital output signal
* pad: off-chip (external) connection
* o: output from chip logic (input to IO cell)
* oe: enable signal for o
*/
class DigitalOutIOCellBundle extends Bundle {
val pad = Output(Bool())
val o = Input(Bool())
val oe = Input(Bool())
}
/** The base IO bundle for a digital input signal
* pad: off-chip (external) connection
* i: input to chip logic (output from IO cell)
* ie: enable signal for i
*/
class DigitalInIOCellBundle extends Bundle {
val pad = Input(Bool())
val i = Output(Bool())
val ie = Input(Bool())
}
trait IOCell extends BaseModule {
var iocell_name: Option[String] = None
/** Set IOCell name
* @param s Proposed name for the IOCell
*
* @return An inherited IOCell with given the proposed name
*/
def suggestName(s: String): this.type = {
iocell_name = Some(s)
super.suggestName(s)
}
}
trait AnalogIOCell extends IOCell {
val io: AnalogIOCellBundle
}
trait DigitalGPIOCell extends IOCell {
val io: DigitalGPIOCellBundle
}
trait DigitalInIOCell extends IOCell {
val io: DigitalInIOCellBundle
}
trait DigitalOutIOCell extends IOCell {
val io: DigitalOutIOCellBundle
}
// The following Generic IO cell black boxes have verilog models that mimic a very simple
// implementation of an IO cell. For building a real chip, it is important to implement
// and use similar classes which wrap the foundry-specific IO cells.
abstract class GenericIOCell extends BlackBox with HasBlackBoxInline {
val impl: String
val moduleName = this.getClass.getSimpleName
setInline(s"$moduleName.v", impl);
}
class GenericAnalogIOCell extends GenericIOCell with AnalogIOCell {
val io = IO(new AnalogIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericAnalogIOCell(
inout pad,
inout core
);
assign core = 1'bz;
assign pad = core;
endmodule"""
}
class GenericDigitalGPIOCell extends GenericIOCell with DigitalGPIOCell {
val io = IO(new DigitalGPIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalGPIOCell(
inout pad,
output i,
input ie,
input o,
input oe
);
assign pad = oe ? o : 1'bz;
assign i = ie ? pad : 1'b0;
endmodule"""
}
class GenericDigitalInIOCell extends GenericIOCell with DigitalInIOCell {
val io = IO(new DigitalInIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalInIOCell(
input pad,
output i,
input ie
);
assign i = ie ? pad : 1'b0;
endmodule"""
}
class GenericDigitalOutIOCell extends GenericIOCell with DigitalOutIOCell {
val io = IO(new DigitalOutIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalOutIOCell(
output pad,
input o,
input oe
);
assign pad = oe ? o : 1'bz;
endmodule"""
}
trait IOCellTypeParams {
def analog(): AnalogIOCell
def gpio(): DigitalGPIOCell
def input(): DigitalInIOCell
def output(): DigitalOutIOCell
}
case class GenericIOCellParams() extends IOCellTypeParams {
def analog() = Module(new GenericAnalogIOCell)
def gpio() = Module(new GenericDigitalGPIOCell)
def input() = Module(new GenericDigitalInIOCell)
def output() = Module(new GenericDigitalOutIOCell)
}
object IOCell {
/** From within a RawModule or MultiIOModule context, generate new module IOs from a given
* signal and return the new IO and a Seq containing all generated IO cells.
* @param coreSignal The signal onto which to add IO cells
* @param name An optional name or name prefix to use for naming IO cells
* @param abstractResetAsAsync When set, will coerce abstract resets to
* AsyncReset, and otherwise to Bool (sync reset)
* @return A tuple of (the generated IO data node, a Seq of all generated IO cell instances)
*/
def generateIOFromSignal[T <: Data](
coreSignal: T,
name: String,
typeParams: IOCellTypeParams = GenericIOCellParams(),
abstractResetAsAsync: Boolean = false
): (T, Seq[IOCell]) = {
val padSignal = IO(DataMirror.internal.chiselTypeClone[T](coreSignal)).suggestName(name)
val resetFn = if (abstractResetAsAsync) toAsyncReset else toSyncReset
val iocells = IOCell.generateFromSignal(coreSignal, padSignal, Some(s"iocell_$name"), typeParams, resetFn)
(padSignal, iocells)
}
/** Connect two identical signals together by adding IO cells between them and return a Seq
* containing all generated IO cells.
* @param coreSignal The core-side (internal) signal onto which to connect/add IO cells
* @param padSignal The pad-side (external) signal onto which to connect IO cells
* @param name An optional name or name prefix to use for naming IO cells
* @return A Seq of all generated IO cell instances
*/
val toSyncReset: (Reset) => Bool = _.asBool
val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset
def generateFromSignal[T <: Data, R <: Reset](
coreSignal: T,
padSignal: T,
name: Option[String] = None,
typeParams: IOCellTypeParams = GenericIOCellParams(),
concretizeResetFn: (Reset) => R = toSyncReset
): Seq[IOCell] = {
def genCell[T <: Data](
castToBool: (T) => Bool,
castFromBool: (Bool) => T
)(coreSignal: T,
padSignal: T
): Seq[IOCell] = {
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => {
val iocell = typeParams.input()
name.foreach(n => {
iocell.suggestName(n)
})
coreSignal := castFromBool(iocell.io.i)
iocell.io.ie := true.B
iocell.io.pad := castToBool(padSignal)
Seq(iocell)
}
case ActualDirection.Output => {
val iocell = typeParams.output()
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.o := castToBool(coreSignal)
iocell.io.oe := true.B
padSignal := castFromBool(iocell.io.pad)
Seq(iocell)
}
case _ => throw new Exception(s"Signal does not have a direction and cannot be matched to an IOCell")
}
}
def genCellForClock = genCell[Clock](_.asUInt.asBool, _.asClock) _
def genCellForAsyncReset = genCell[AsyncReset](_.asBool, _.asAsyncReset) _
def genCellForAbstractReset = genCell[Reset](_.asBool, concretizeResetFn) _
(coreSignal, padSignal) match {
case (coreSignal: Analog, padSignal: Analog) => {
if (coreSignal.getWidth == 0) {
Seq()
} else {
require(
coreSignal.getWidth == 1,
"Analogs wider than 1 bit are not supported because we can't bit-select Analogs (https://github.com/freechipsproject/chisel3/issues/536)"
)
val iocell = typeParams.analog()
name.foreach(n => iocell.suggestName(n))
iocell.io.core <> coreSignal
padSignal <> iocell.io.pad
Seq(iocell)
}
}
case (coreSignal: Clock, padSignal: Clock) => genCellForClock(coreSignal, padSignal)
case (coreSignal: AsyncReset, padSignal: AsyncReset) => genCellForAsyncReset(coreSignal, padSignal)
case (coreSignal: Bits, padSignal: Bits) => {
require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width")
if (padSignal.getWidth == 0) {
// This dummy assignment will prevent invalid firrtl from being emitted
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => coreSignal := 0.U
case _ => {}
}
Seq()
} else {
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => {
val iocells = padSignal.asBools.zipWithIndex.map { case (sig, i) =>
val iocell = typeParams.input()
// Note that we are relying on chisel deterministically naming this in the index order (which it does)
// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
// An alternative solution would be to suggestName(n + "_" + i)
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.pad := sig
iocell.io.ie := true.B
iocell
}
// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
coreSignal := Cat(iocells.map(_.io.i).reverse)
iocells
}
case ActualDirection.Output => {
val iocells = coreSignal.asBools.zipWithIndex.map { case (sig, i) =>
val iocell = typeParams.output()
// Note that we are relying on chisel deterministically naming this in the index order (which it does)
// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
// An alternative solution would be to suggestName(n + "_" + i)
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.o := sig
iocell.io.oe := true.B
iocell
}
// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
padSignal := Cat(iocells.map(_.io.pad).reverse)
iocells
}
case _ => throw new Exception("Bits signal does not have a direction and cannot be matched to IOCell(s)")
}
}
}
case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal)
case (coreSignal: Vec[_], padSignal: Vec[_]) => {
require(padSignal.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same")
coreSignal.zip(padSignal).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) =>
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + i), typeParams)
total ++ ios
}
}
case (coreSignal: Record, padSignal: Record) => {
coreSignal.elements.foldLeft(Seq.empty[IOCell]) { case (total, (eltName, core)) =>
val pad = padSignal.elements(eltName)
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + eltName), typeParams)
total ++ ios
}
}
case _ => { throw new Exception("Oops, I don't know how to handle this signal.") }
}
}
}

2
generators/diplomacy

Submodule generators/diplomacy updated: edf375300d...055be698f4

2
generators/fft-generator

Submodule generators/fft-generator updated: 490b975d36...6a6413b526

2
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -26,7 +26,7 @@ import firesim.configs.MemModelKey
import tracegen.{TraceGenSystemModuleImp}
import cva6.CVA6Tile
import barstools.iocell.chisel._
import chipyard.iocell._
import chipyard.iobinders._
import chipyard._
import chipyard.harness._

8
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -367,3 +367,11 @@ class FireSimRadianceClusterSynConfig extends Config(
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.RadianceClusterSynConfig)
class FireSimLargeBoomSV39CospikeConfig extends Config(
new firesim.firesim.WithCospikeBridge ++
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks++
new chipyard.config.WithSV39 ++
new chipyard.LargeBoomV3Config)

2
generators/gemmini

Submodule generators/gemmini updated: 5bcbead0ad...8a9c423900

1
generators/hwacha

Submodule generators/hwacha deleted from bf799dc482

2
generators/ibex

Submodule generators/ibex updated: c2174aba4f...89c19c2d7b

2
generators/icenet

Submodule generators/icenet updated: ab30e23e8e...969bc8f9a0

2
generators/mempress

Submodule generators/mempress updated: 415f55b583...0b362f9031

2
generators/riscv-sodor

Submodule generators/riscv-sodor updated: bbfc3c3510...ca0431493e

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 8c8b3f5dcf...cf654499ab

2
generators/rocket-chip-inclusive-cache

Submodule generators/rocket-chip-inclusive-cache updated: 1332d2268a...45d184f2fd

1
generators/sha3

Submodule generators/sha3 deleted from 2d38585d64

31
scripts/build-setup.sh
View File

@@ -12,11 +12,10 @@ source $CYDIR/scripts/utils.sh
common_setup
usage() {
echo "Usage: ${0} [OPTIONS] [riscv-tools | esp-tools]"
echo "Usage: ${0} [OPTIONS] [riscv-tools]"
echo ""
echo "Installation Types"
echo " riscv-tools: if set, builds the riscv toolchain (this is also the default)"
echo " esp-tools: if set, builds esp-tools toolchain used for the hwacha vector accelerator"
echo ""
echo "Helper script to fully initialize repository that wraps other scripts."
echo "By default it initializes/installs things in the following order:"
@@ -69,7 +68,7 @@ do
case $1 in
-h | --help )
usage 3 ;;
riscv-tools | esp-tools)
riscv-tools )
TOOLCHAIN_TYPE=$1 ;;
--verbose | -v)
VERBOSE_FLAG=$1
@@ -119,29 +118,6 @@ run_step() {
{
# esp-tools should ONLY be used for hwacha.
# Check for this, since many users will be attempting to use this with gemmini
if [ $TOOLCHAIN_TYPE == "esp-tools" ]; then
while true; do
printf '\033[2J'
read -p "WARNING: You are trying to install the esp-tools toolchain."$'\n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate
case "$validate" in
y | Y)
echo "Installing esp-tools."
break
;;
n | N)
error "Rerun with riscv-tools"
exit 3
;;
*)
error "Invalid response. Please type \"y\" or \"n\""
;;
esac
done
fi
#######################################
###### BEGIN STEP-BY-STEP SETUP #######
#######################################
@@ -271,7 +247,8 @@ if run_step "6"; then
echo $CYDIR
source sourceme-manager.sh --skip-ssh-setup
pushd sim
make sbt SBT_COMMAND="project {file:$CYDIR}firechip; compile" TARGET_PROJECT=firesim
make target-classpath
make firesim-main-classpath
popd
)
exit_if_last_command_failed

5
scripts/build-toolchain-extra.sh
View File

@@ -16,11 +16,10 @@ common_setup
readonly MAKE
usage() {
echo "usage: ${0} [OPTIONS] [riscv-tools | esp-tools]"
echo "usage: ${0} [OPTIONS] [riscv-tools]"
echo ""
echo "Installation Types"
echo " riscv-tools: if set, builds the riscv toolchain (this is also the default)"
echo " esp-tools: if set, builds esp-tools toolchain used for the hwacha vector accelerator"
echo ""
echo "Options"
echo " --prefix -p PREFIX : Install destination."
@@ -45,7 +44,7 @@ do
RISCV=$(realpath $1) ;;
--clean-after-install )
CLEANAFTERINSTALL="true" ;;
riscv-tools | esp-tools)
riscv-tools )
TOOLCHAIN=$1 ;;
* )
error "invalid option $1"

2
scripts/generate-conda-lockfiles.sh
View File

@@ -10,7 +10,7 @@ if [ ! -d "$REQS_DIR" ]; then
exit 1
fi
for TOOLCHAIN_TYPE in riscv-tools esp-tools; do
for TOOLCHAIN_TYPE in riscv-tools; do
# note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154
LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml
rm -rf $LOCKFILE

4
scripts/init-submodules-no-riscv-tools-nolog.sh
View File

@@ -72,7 +72,6 @@ cd "$RDIR"
generators/cva6 \
generators/nvdla \
toolchains/libgloss \
generators/sha3 \
generators/gemmini \
generators/rocket-chip \
sims/firesim \
@@ -101,9 +100,6 @@ cd "$RDIR"
)
(
# Non-recursive clone to exclude riscv-linux
git submodule update --init generators/sha3
# Non-recursive clone to exclude cva6 submods
git submodule update --init generators/cva6
git -C generators/cva6 submodule update --init src/main/resources/cva6/vsrc/cva6

3
scripts/repo-clean.sh
View File

@@ -9,9 +9,6 @@ rm -rf $RDIR/toolchains/libgloss/build.log
rm -rf $RDIR/toolchains/riscv-tools/riscv-isa-sim/build.log
rm -rf $RDIR/toolchains/riscv-tools/riscv-pk/build.log
rm -rf $RDIR/toolchains/riscv-tools/riscv-tests/build.log
rm -rf $RDIR/toolchains/esp-tools/riscv-isa-sim/build.log
rm -rf $RDIR/toolchains/esp-tools/riscv-pk/build.log
rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log
(
pushd $RDIR/generators/constellation
if [ -d espresso ]

5
scripts/split-mems-conf.py
View File

@@ -70,7 +70,10 @@ if __name__ == "__main__":
imhj_data = json.load(imhj)
dut_root = bfs_find_root(imhj_data, args.dut_module_name)
dut_submodules = bfs_collect_submodules(dut_root)
if dut_root:
dut_submodules = bfs_collect_submodules(dut_root)
else:
dut_submodules = set()
model_root = bfs_find_root(imhj_data, args.model_module_name)
model_submodules = bfs_collect_submodules(model_root)

28
scripts/tutorial-patches/build.sbt.patch
View File

@@ -1,28 +0,0 @@
diff --git a/build.sbt b/build.sbt
index c3be6161..2a6d7160 100644
--- a/build.sbt
+++ b/build.sbt
@@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
+ //sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, rocket_dsp_utils,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
constellation, mempress, barf, shuttle, caliptra_aes)
@@ -219,10 +219,10 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
-lazy val sha3 = (project in file("generators/sha3"))
- .dependsOn(rocketchip, midasTargetUtils)
- .settings(libraryDependencies ++= rocketLibDeps.value)
- .settings(commonSettings)
+// lazy val sha3 = (project in file("generators/sha3"))
+// .dependsOn(rocketchip, midasTargetUtils)
+// .settings(libraryDependencies ++= rocketLibDeps.value)
+// .settings(commonSettings)
lazy val gemmini = (project in file("generators/gemmini"))
.dependsOn(rocketchip)

16
scripts/tutorial-setup.sh
View File

@@ -1,16 +0,0 @@
#!/bin/bash
set -ex
RDIR=$(git rev-parse --show-toplevel)
cd $RDIR
git rm generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
git rm -rf generators/sha3
for p in scripts/tutorial-patches/*.patch
do
echo "Applying tutorial patch $p"
git apply $p
done

12
sims/common-sim-flags.mk
View File

@@ -2,17 +2,9 @@
# common gcc configuration/optimization
#----------------------------------------------------------------------------------------
SIM_OPT_CXXFLAGS := -O3
# Workaround: esp-isa-sim doesn't install libriscv,
# so don't link with libriscv if it doesn't exist
# potentially breaks some configs
ifeq (,$(wildcard $(RISCV)/lib/libriscv.so))
$(warning libriscv not found)
LRISCV=
else
LRISCV=-lriscv
endif
export USE_CHISEL6=1
SIM_CXXFLAGS = \
$(CXXFLAGS) \

2
sims/firesim

Submodule sims/firesim updated: ac8bcd8b34...1f62b3ef15

2
software/firemarshal

Submodule software/firemarshal updated: a98f1faff6...b014183ac6

1
toolchains/esp-tools/esp-tools-feedstock

Submodule toolchains/esp-tools/esp-tools-feedstock deleted from 76a16c8ddb

1
toolchains/esp-tools/riscv-isa-sim

Submodule toolchains/esp-tools/riscv-isa-sim deleted from 34741e07bc

1
toolchains/esp-tools/riscv-pk

Submodule toolchains/esp-tools/riscv-pk deleted from e8e6b3aaee

1
toolchains/esp-tools/riscv-tests

Submodule toolchains/esp-tools/riscv-tests deleted from 7c3dfd3205

2
toolchains/libgloss

Submodule toolchains/libgloss updated: 39234a1624...0ecdf7fa08

2
toolchains/riscv-tools/riscv-isa-sim

Submodule toolchains/riscv-tools/riscv-isa-sim updated: 4d8651be94...e46fc096e2

2
toolchains/riscv-tools/riscv-pk

Submodule toolchains/riscv-tools/riscv-pk updated: e8e6b3aaee...e681d8088b

2
toolchains/riscv-tools/riscv-spike-devices

Submodule toolchains/riscv-tools/riscv-spike-devices updated: 39a0993b20...cc184f2cc1

2
toolchains/riscv-tools/riscv-tools-feedstock

Submodule toolchains/riscv-tools/riscv-tools-feedstock updated: 56c29e01ba...917b56ef1a

1
tools/barstools

Submodule tools/barstools deleted from 60a1be9bfe

2
tools/cde

Submodule tools/cde updated: 384c06b8d4...2bcaeae2b9

2
tools/dsptools

Submodule tools/dsptools updated: 8f43366395...a310a157ca

1
tools/dsptools-chisel3 Submodule

Submodule tools/dsptools-chisel3 added at 8f43366395

2
tools/fixedpoint

Submodule tools/fixedpoint updated: 36ce43c90c...ef164009e4

1
tools/fixedpoint-chisel3 Submodule

Submodule tools/fixedpoint-chisel3 added at 36ce43c90c

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