Bump rocket-chip to standalone diplomacy

2024-03-10 12:16:12 -07:00
parent b592934402
commit a27bc7f5ed
32 changed files with 88 additions and 63 deletions
--- a/.github/scripts/check-commit.sh
+++ b/.github/scripts/check-commit.sh
@@ -45,7 +45,7 @@ search () {
    done
 }

-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
+submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
 dir="generators"
 branches=("master" "main" "dev")
 search
--- a/.gitmodules
+++ b/.gitmodules
@@ -16,6 +16,9 @@
 [submodule "generators/cva6"]
 	path = generators/cva6
 	url = https://github.com/ucb-bar/cva6-wrapper.git
+[submodule "generators/diplomacy"]
+	path = generators/diplomacy
+	url = https://github.com/chipsalliance/diplomacy.git
 [submodule "generators/fft-generator"]
 	path = generators/fft-generator
 	url = https://github.com/ucb-bar/FFTGenerator.git
--- a/build.sbt
+++ b/build.sbt
@@ -113,8 +113,19 @@ lazy val rocketMacros  = (project in rocketChipDir / "macros")
    )
  )

+lazy val diplomacy = freshProject("diplomacy", file("generators/diplomacy/diplomacy"))
+  .dependsOn(cde)
+  .settings(commonSettings)
+  .settings(chiselSettings)
+  .settings(Compile / scalaSource := baseDirectory.value / "diplomacy")
+  .settings(
+    libraryDependencies ++= Seq(
+      "com.lihaoyi" %% "sourcecode" % "0.3.1"
+    )
+  )
+
 lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
-  .dependsOn(hardfloat, rocketMacros, cde)
+  .dependsOn(hardfloat, rocketMacros, diplomacy, cde)
  .settings(commonSettings)
  .settings(chiselSettings)
  .settings(
@@ -123,7 +134,8 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
      "org.json4s" %% "json4s-jackson" % "4.0.5",
      "org.scalatest" %% "scalatest" % "3.2.0" % "test",
-      "org.scala-graph" %% "graph-core" % "1.13.5"
+      "org.scala-graph" %% "graph-core" % "1.13.5",
+      "com.lihaoyi" %% "sourcecode" % "0.3.1"
    )
  )
  .settings( // Settings for scalafix
--- a/fpga/fpga-shells
+++ b/fpga/fpga-shells
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -5,7 +5,7 @@ import chisel3._
 import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 import freechips.rocketchip.jtag.{JTAGIO}

-import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
+import sifive.blocks.devices.uart.{UARTPortIO}
 import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
 import sifive.blocks.devices.pinctrl.{BasePin}

--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -5,7 +5,8 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.system._
 import freechips.rocketchip.tile._

--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -5,10 +5,9 @@ import chisel3._
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem.{PeripheryBusKey}
 import freechips.rocketchip.tilelink.{TLBundle}
-import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
-
-import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
+import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
+import sifive.blocks.devices.uart.{UARTPortIO, UARTParams}
 import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
 import sifive.blocks.devices.pinctrl.{BasePin}
 import sifive.fpgashells.shell._
--- a/fpga/src/main/scala/nexysvideo/Configs.scala
+++ b/fpga/src/main/scala/nexysvideo/Configs.scala
@@ -5,7 +5,7 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.system._
 import freechips.rocketchip.tile._

--- a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
+++ b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
@@ -7,6 +7,7 @@ import freechips.rocketchip.subsystem.{PeripheryBusKey}
 import freechips.rocketchip.tilelink.{TLBundle}
 import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
+import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}

 import sifive.blocks.devices.uart.{UARTParams}

--- a/fpga/src/main/scala/vc707/HarnessBinders.scala
+++ b/fpga/src/main/scala/vc707/HarnessBinders.scala
@@ -3,10 +3,10 @@ package chipyard.fpga.vc707
 import chisel3._
 import chisel3.experimental.{BaseModule}

-import freechips.rocketchip.util.{HeterogeneousBag}
+import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
 import freechips.rocketchip.tilelink.{TLBundle}

-import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
+import sifive.blocks.devices.uart.{UARTPortIO}
 import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
 import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{HasSystemXilinxVC707PCIeX1ModuleImp, XilinxVC707PCIeX1IO}

--- a/fpga/src/main/scala/vcu118/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala
@@ -3,10 +3,10 @@ package chipyard.fpga.vcu118
 import chisel3._
 import chisel3.experimental.{BaseModule}

-import freechips.rocketchip.util.{HeterogeneousBag}
+import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
 import freechips.rocketchip.tilelink.{TLBundle}

-import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
+import sifive.blocks.devices.uart.{UARTPortIO}
 import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}

 import chipyard._
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -43,12 +43,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
  override lazy val module = new DigitalTopModule(this)
 }

-class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
-  with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
-  with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
-  with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
-  with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
-  with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
-  with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
+class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l)
  with freechips.rocketchip.util.DontTouch
 // DOC include end: DigitalTop
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -121,6 +121,6 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
 }

 class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
-    with HasHierarchicalElementsRootContextModuleImp
-{
+    with HasHierarchicalElementsRootContextModuleImp {
+  override lazy val outer = _outer
 }
--- a/generators/chipyard/src/main/scala/System.scala
+++ b/generators/chipyard/src/main/scala/System.scala
@@ -38,7 +38,7 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
 /**
 * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
 */
-class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer)
+class ChipyardSystemModule(_outer: ChipyardSystem) extends ChipyardSubsystemModuleImp(_outer)
  with HasRTCModuleImp
  with HasExtInterruptsModuleImp
  with DontTouch
@@ -60,6 +60,7 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
  private val portName = "tl_mem"
  private val device = new MemoryDevice
  private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
+  private val mbus = tlBusWrapperLocationMap.lift(MBUS).getOrElse(locateTLBusWrapper(SBUS))

  val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) =>
    Seq.tabulate(nMemoryChannels) { channel =>
@@ -76,15 +77,15 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
         supportsPutFull    = TransferSizes(1, mbus.blockBytes),
         supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
         beatBytes = memPortParams.beatBytes)
-   }
- }).toList.flatten)
+    }
+  }).toList.flatten)

- mbus.coupleTo(s"memory_controller_port_named_$portName") {
-   (memTLNode
-     :*= TLBuffer()
-     :*= TLSourceShrinker(1 << idBits)
-     :*= TLWidthWidget(mbus.beatBytes)
-     :*= _)
+  mbus.coupleTo(s"memory_controller_port_named_$portName") {
+    (memTLNode
+      :*= TLBuffer()
+      :*= TLSourceShrinker(1 << idBits)
+      :*= TLWidthWidget(mbus.beatBytes)
+      :*= _)
  }

  val mem_tl = InModuleBody { memTLNode.makeIOs() }
--- a/generators/chipyard/src/main/scala/example/CustomChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala
@@ -67,13 +67,13 @@ class WithCustomChipTop extends Config((site, here, up) => {
 })

 class WithBrokenOutUARTIO extends OverrideIOBinder({
-  (system: HasPeripheryUARTModuleImp) => {
+  (system: HasPeripheryUART) => {
    val uart_txd = IO(Output(Bool()))
    val uart_rxd = IO(Input(Bool()))
    system.uart(0).rxd := uart_rxd
    uart_txd := system.uart(0).txd
    val where = PBUS // TODO fix
-    val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+    val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
    val freqMHz = bus.dtsFrequency.get / 1000000
    (Seq(UARTPort(() => {
      val uart_wire = Wire(new UARTPortIO(system.uart(0).c))
--- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
@@ -145,7 +145,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
    // UART
    //==========================
    require(system.uarts.size == 1)
-    val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
+    val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.uart.head, "uart_0", p(IOCellKey))
    val where = PBUS // TODO fix
    val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
    val freqMHz = bus.dtsFrequency.get / 1000000
--- a/generators/chipyard/src/main/scala/example/GCD.scala
+++ b/generators/chipyard/src/main/scala/example/GCD.scala
@@ -5,7 +5,7 @@ import chisel3.util._
 import chisel3.experimental.{IntParam, BaseModule}
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.prci._
-import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.subsystem.{BaseSubsystem, PBUS}
 import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper.{HasRegMap, RegField}
@@ -194,6 +194,8 @@ class GCDAXI4(params: GCDParams, beatBytes: Int)(implicit p: Parameters) extends
 trait CanHavePeripheryGCD { this: BaseSubsystem =>
  private val portName = "gcd"

+  private val pbus = locateTLBusWrapper(PBUS)
+
  // Only build if we are using the TL (nonAXI4) version
  val gcd_busy = p(GCDKey) match {
    case Some(params) => {
--- a/generators/chipyard/src/main/scala/example/InitZero.scala
+++ b/generators/chipyard/src/main/scala/example/InitZero.scala
@@ -2,7 +2,7 @@ package chipyard.example

 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
+import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes, FBUS}
 import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
 import freechips.rocketchip.tilelink._
@@ -62,6 +62,7 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem =>

  p(InitZeroKey) .map { k =>
    val initZero = LazyModule(new InitZero()(p))
+    val fbus = locateTLBusWrapper(FBUS)
    fbus.coupleFrom("init-zero") { _ := initZero.node }
  }
 }
--- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
@@ -199,6 +199,7 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p
 trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
  val streamingFIR = p(GenericFIRKey) match {
    case Some(params) => {
+      val pbus = locateTLBusWrapper(PBUS)
      val domain = pbus.generateSynchronousDomain.suggestName("fir_domain")
      val streamingFIR = domain { LazyModule(new TLGenericFIRChain(
        genIn = FixedPoint(8.W, 3.BP),
--- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
@@ -131,6 +131,7 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
 trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
  val passthrough = p(StreamingPassthroughKey) match {
    case Some(params) => {
+      val pbus = locateTLBusWrapper(PBUS)
      val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain")
      val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) }
      pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ }
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -5,7 +5,12 @@ import chisel3.reflect.DataMirror
 import chisel3.experimental.Analog

 import org.chipsalliance.cde.config._
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy._
+import org.chipsalliance.diplomacy.nodes._
+import org.chipsalliance.diplomacy.aop._
+import org.chipsalliance.diplomacy.lazymodule._
+import org.chipsalliance.diplomacy.bundlebridge._
+import freechips.rocketchip.diplomacy.{Resource, ResourceBinding, ResourceAddress}
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem._
@@ -165,11 +170,12 @@ case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams())


 class WithGPIOCells extends OverrideIOBinder({
-  (system: HasPeripheryGPIOModuleImp) => {
+  (system: HasPeripheryGPIO) => {
    val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) =>
      gpio.pins.zipWithIndex.map({ case (pin, j) =>
+        val p = system.asInstanceOf[BaseSubsystem].p
        val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}")
-        val iocell = system.p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
+        val iocell = p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
        iocell.io.o := pin.o.oval
        iocell.io.oe := pin.o.oe
        iocell.io.ie := pin.o.ie
@@ -184,7 +190,7 @@ class WithGPIOCells extends OverrideIOBinder({
 })

 class WithGPIOPunchthrough extends OverrideIOBinder({
-  (system: HasPeripheryGPIOModuleImp) => {
+  (system: HasPeripheryGPIO) => {
    val ports = system.gpio.zipWithIndex.map { case (gpio, i) =>
      val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i")
      io_gpio <> gpio
@@ -195,7 +201,7 @@ class WithGPIOPunchthrough extends OverrideIOBinder({
 })

 class WithI2CPunchthrough extends OverrideIOBinder({
-  (system: HasPeripheryI2CModuleImp) => {
+  (system: HasPeripheryI2C) => {
    val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
      val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
      io_i2c <> i2c
@@ -207,11 +213,12 @@ class WithI2CPunchthrough extends OverrideIOBinder({

 // DOC include start: WithUARTIOCells
 class WithUARTIOCells extends OverrideIOBinder({
-  (system: HasPeripheryUARTModuleImp) => {
+  (system: HasPeripheryUART) => {
    val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
-      val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true)
+      val p = system.asInstanceOf[BaseSubsystem].p
+      val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", p(IOCellKey), abstractResetAsAsync = true)
      val where = PBUS // TODO fix
-      val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+      val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
      val freqMHz = bus.dtsFrequency.get / 1000000
      (UARTPort(() => port, i, freqMHz.toInt), ios)
    }).unzip
@@ -227,7 +234,7 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
      Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
    }
    InModuleBody {
-      val spi = system.asInstanceOf[BaseSubsystem].module.asInstanceOf[HasPeripherySPIBundle].spi
+      val spi = system.spi
      val ports = spi.zipWithIndex.map({ case (s, i) =>
        val io_spi = IO(s.cloneType).suggestName(s"spi_$i")
        io_spi <> s
@@ -239,20 +246,20 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
 })

 class WithSPIFlashIOCells extends OverrideIOBinder({
-  (system: HasPeripherySPIFlashModuleImp) => {
+  (system: HasPeripherySPIFlash) => {
    val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
-
+      val p = system.asInstanceOf[BaseSubsystem].p
      val name = s"spi_${i}"
      val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
      val iocellBase = s"iocell_${name}"

      // SCK and CS are unidirectional outputs
-      val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey), IOCell.toAsyncReset)
-      val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey), IOCell.toAsyncReset)
+      val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), p(IOCellKey), IOCell.toAsyncReset)
+      val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), p(IOCellKey), IOCell.toAsyncReset)

      // DQ are bidirectional, so then need special treatment
      val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>
-        val iocell = system.p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
+        val iocell = p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
        iocell.io.o := pin.o
        iocell.io.oe := pin.oe
        iocell.io.ie := true.B
@@ -261,7 +268,7 @@ class WithSPIFlashIOCells extends OverrideIOBinder({
        iocell
      }

-      (SPIFlashPort(() => port, system.p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
+      (SPIFlashPort(() => port, p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
    }).unzip
    (ports, cells2d.flatten)
  }
@@ -419,7 +426,8 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
  (system: CanHaveSlaveAXI4Port) => {
    implicit val p: Parameters = GetSystemParameters(system)
    val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
-    clockSinkNode.map(_ := system.asInstanceOf[BaseSubsystem].fbus.fixedClockNode)
+    val fbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(FBUS)
+    clockSinkNode.map(_ := fbus.fixedClockNode)
    def clockBundle = clockSinkNode.get.in.head._1

    InModuleBody {
--- a/generators/chipyard/src/main/scala/iobinders/Ports.scala
+++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala
@@ -16,8 +16,8 @@ import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters}
 import freechips.rocketchip.subsystem.{MemoryPortParams, MasterPortParams, SlavePortParams}
 import freechips.rocketchip.devices.debug.{ClockedDMIIO}
-import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.tilelink.{TLBundle}
+import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}

 trait Port[T <: Data] {
  val getIO: () => T
--- a/generators/diplomacy
+++ b/generators/diplomacy
--- a/generators/fft-generator
+++ b/generators/fft-generator
--- a/generators/nvdla
+++ b/generators/nvdla
--- a/generators/rocc-acc-utils
+++ b/generators/rocc-acc-utils
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
--- a/generators/rocket-chip-blocks
+++ b/generators/rocket-chip-blocks
--- a/generators/testchipip
+++ b/generators/testchipip
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -23,7 +23,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
    case t: boom.v4.lsu.BoomTraceGenTile => t.statusNode.makeSink()
  }

-  lazy val fakeClockDomain = sbus.generateSynchronousDomain
+  lazy val fakeClockDomain = locateTLBusWrapper("sbus").generateSynchronousDomain

  lazy val clintOpt = None
  lazy val debugOpt = None
--- a/sims/firesim
+++ b/sims/firesim
--- a/tools/rocket-dsp-utils
+++ b/tools/rocket-dsp-utils