E2E RocketConfig compile in Verilator

2022-10-08 10:42:06 -07:00
parent ae05fe0de2
commit a384fa9d1d
5 changed files with 118 additions and 36 deletions
--- a/common.mk
+++ b/common.mk
@@ -157,6 +157,15 @@ $(CIRCT_TARGETS): firrtl_temp
 	@echo "" > /dev/null

 firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
+	$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTop,\
+		--input-file $(FIRRTL_FILE) \
+		--annotation-file $(ANNO_FILE) \
+		--out-fir-file $(INT_FIR) \
+		--out-anno-file $(INT_ANNO) \
+		--log-level $(FIRRTL_LOGLEVEL) \
+		--allow-unrecognized-annotations \
+		-X none \
+		$(EXTRA_FIRRTL_OPTIONS))
 	$(SCRATCH_HOME)/circt/build/bin/firtool \
 		--export-module-hierarchy \
 		--emit-metadata \
@@ -164,7 +173,7 @@ firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
 		-warn-on-unprocessed-annotations \
 		-verify-each=false \
 		-dedup \
-		--annotation-file=$(ANNO_FILE) \
+		--annotation-file=$(INT_ANNO) \
 		--disable-annotation-classless \
 		--disable-annotation-unknown \
 		--lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \
@@ -173,13 +182,16 @@ firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
 		--repl-seq-mem-file=$(VSRC_SMEMS_CONF) \
 		--split-verilog \
 		-o $(VSRC_DUMP) \
-		$(FIRRTL_FILE)
-#	touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
+		$(INT_FIR)
+	sed -i 's/.*/& /' $(VSRC_SMEMS_CONF)
 # DOC include end: FirrtlCompiler

-$(TOP_MODS_FILE) $(HARNESS_MODS_FILE): $(VSRC_MODH_JSON)
-	$(base_dir)/scripts/dump-mods.py $(TOP) $^ > $(TOP_MODS_FILE)
-	$(base_dir)/scripts/dump-mods.py $(MODEL) $^ > $(HARNESS_MODS_FILE)
+$(TOP_MODS_FILE) $(ALL_MODS_FILE): $(VSRC_MODH_JSON) $(VSRC_FILELIST)
+	$(base_dir)/scripts/dump-mods.py --dut-top $(TOP) --hier-json $(VSRC_MODH_JSON) --dut-mods $(TOP_MODS_FILE) --filelist $(VSRC_FILELIST) --build_dir $(VSRC_DUMP)
+	sed -e 's;^;$(VSRC_DUMP)/;' $(VSRC_FILELIST) > $(ALL_MODS_FILE)
+
+.PHONY: temp
+temp: $(TOP_MODS_FILE)

 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
 MACROCOMPILER_MODE ?= --mode synflops
@@ -193,8 +205,9 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR) &: $(HARNESS_SMEMS_CONF) | $(TOP_SMEM
 ########################################################################################
 # remove duplicate files and headers in list of simulation file inputs
 ########################################################################################
-$(sim_common_files): $(sim_files)
-	sort -u $^ | grep -v '.*\.\(svh\|h\)$$' > $@
+$(sim_common_files): $(sim_files) $(ALL_MODS_FILE) $(VSRC_SMEMS_FILE)
+	sort -u $(sim_files) $(ALL_MODS_FILE) | grep -v '.*\.\(svh\|h\)$$' > $@
+	echo "$(VSRC_SMEMS_FILE)" >> $@

 #########################################################################################
 # helper rule to just make verilog files
--- a/scripts/dump-mods.py
+++ b/scripts/dump-mods.py
@@ -1,18 +1,84 @@
-#!/usr/bin/python
-
-# dump all modules (deduped) given a specific module
-#
-# args
-# $1 - module to dump all modules underneath (inclusive)
-# $2 - module heirarchy file
-
-import sys
+#!/usr/bin/env python
 import json
+import argparse
+from typing import List, Optional
+# Schema of json emitted by circt
+"""
+{
+  "instance_name": "TestHarness",
+  "module_name": "TestHarness",
+  "instances": [
+    {
+      "instance_name": "chiptop",
+      "module_name": "ChipTop",
+      "instances": [
+        {
+          "instance_name": "system",
+          "module_name": "DigitalTop",
+          "instances": [ ]
+        }, ...
+      ]
+    },
+    {
+      "instance_name": "simdram",
+      "module_name": "SimDRAM",
+      "instances": []
+    },
+  ]
+}
+"""
+def get_modules(js: dict) -> List[str]:
+    if 'instances' not in js:
+        return js['module_name']
+    else:
+        mods = []
+        for mod in js['instances']:
+            mods.extend(get_modules(mod))
+        return [js['module_name']] + mods
+def find_mod_by_name(js: dict, name: str) -> Optional[List[dict]]:
+    if 'instances' not in js:
+        return None
+    else:
+        mods = []
+        for mod in js['instances']:
+            if mod['module_name'] == name:
+                mods.append(mod)
+            other_mods = find_mod_by_name(mod, name)
+            if other_mods is not None:
+                mods.extend(other_mods)
+        return mods
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(description='Convert circt hierarchy json into DUT and test harness filelists')
+    parser.add_argument('--hier-json', type=str, required=True, help='path to hierarchy JSON emitted by firtool')
+    parser.add_argument('--dut-top', type=str, required=True, help='name of the DUT top-level module')
+    parser.add_argument('--filelist', type=str, required=True, help='input filelist')
+    parser.add_argument('--build_dir', type=str, required=True, help='build_dir')
+    parser.add_argument('--dut-mods', type=str, required=True, help='dut mods')
+    args = parser.parse_args()
+    with open(args.hier_json) as f:
+        j = json.load(f)
+        dut_tops = find_mod_by_name(j, args.dut_top)
+        assert dut_tops is not None
+        assert len(dut_tops) == 1
+        dut_top = dut_tops[0]
+        dut_mods = set(get_modules(dut_top))
+        tb_mods = set(get_modules(j)) - dut_mods
+        both_mods = dut_mods.intersection(tb_mods)
+        #print(dut_mods)
+        #print(tb_mods)
+        #print(both_mods)
+        assert len(both_mods) == 0


-mod_name = sys.argv[1]
-mod_file = sys.argv[2]
+        with open(args.dut_mods, 'w') as df:
+            with open(args.filelist) as fl:
+                for path in fl:
+                    writeOut = True
+                    for dm in dut_mods:
+                        if dm in path:
+                            # don't write
+                            writeOut = False
+                            break

-# open file
-with open(mod_file, 'r') as modFile:
-    #print(json.load(modFile))
+                    if writeOut:
+                        df.write(f"{args.build_dir}/{path}")
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -50,7 +50,7 @@ SIM_FILE_REQS += \
 	$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
 	$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \

-# the following files are needed for emulator.cc to compile
+# the following files are needed for emulator.cc to compile (even if they aren't included in RTL)
 SIM_FILE_REQS += \
 	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \
 	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \
@@ -168,8 +168,7 @@ VERILATOR_NONCC_OPTS = \
 	$(PREPROC_DEFINES) \
 	--top-module $(VLOG_MODEL) \
 	--vpi \
-	-f $(sim_common_files) \
-	$(sim_vsrcs)
+	-f $(sim_common_files)

 #----------------------------------------------------------------------------------------
 # gcc configuration/optimization
@@ -210,13 +209,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
 #########################################################################################
 # build makefile fragment that builds the verilator sim rules
 #########################################################################################
-$(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
+$(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir)
 	mkdir -p $(model_dir)
 	$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
 	touch $@

-$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
+$(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir_debug)
 	mkdir -p $(model_dir_debug)
 	$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
--- a/tools/barstools
+++ b/tools/barstools
--- a/variables.mk
+++ b/variables.mk
@@ -146,16 +146,22 @@ endif
 FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
 ANNO_FILE   ?= $(build_dir)/$(long_name).anno.json

-VSRC_DUMP ?= $(build_dir)/vsrc
+INT_FIR ?= $(build_dir)/$(long_name).intermediate.fir
+INT_ANNO ?= $(build_dir)/$(long_name).intermediate.anno.json
+
+VSRC_DUMP ?= $(build_dir)
 VSRC_SMEMS_CONF ?= $(VSRC_DUMP)/$(long_name).mems.conf
 VSRC_MODH_JSON ?= $(VSRC_DUMP)/mod-he.json

-VSRC_SMEMS_FILE ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).mems.v
-VSRC_SMEMS_FIR  ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).mems.fir
+VSRC_FILELIST ?= $(VSRC_DUMP)/filelist.f
+VSRC_BB_F ?= $(VSRC_DUMP)/firrtl_black_box_resource_files.json
+
+VSRC_SMEMS_FILE ?= $(VSRC_DUMP)/$(long_name).mems.v
+VSRC_SMEMS_FIR  ?= $(VSRC_DUMP)/$(long_name).mems.fir

 # top only modules
-TOP_MODS_FILE ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).top.f
-HARNESS_MODS_FILE ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).top.f
+TOP_MODS_FILE ?= $(VSRC_DUMP)/$(long_name).top.f
+ALL_MODS_FILE ?= $(VSRC_DUMP)/$(long_name).all.f

 BOOTROM_FILES   ?= bootrom.rv64.img bootrom.rv32.img
 BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
@@ -163,8 +169,6 @@ BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
 # files that contain lists of files needed for VCS or Verilator simulation
 SIM_FILE_REQS =
 sim_files              ?= $(build_dir)/sim_files.f
-sim_top_blackboxes     ?= $(build_dir)/firrtl_black_box_resource_files.top.f
-sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
 # single file that contains all files needed for VCS or Verilator simulation (unique and without .h's)
 sim_common_files       ?= $(build_dir)/sim_files.common.f

@@ -199,7 +203,7 @@ define run_scala_main
 	cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)"
 endef

-FIRRTL_LOGLEVEL ?= error
+FIRRTL_LOGLEVEL ?= debug

 #########################################################################################
 # output directory for tests