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Closer [ci skip]

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This commit is contained in:
abejgonzalez
2022-10-04 08:43:20 -07:00
committed by joey0320
parent 873131c0c7
commit ae05fe0de2
4 changed files with 32 additions and 18 deletions
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11
common.mk
View File

@@ -126,7 +126,7 @@ firrtl: $(FIRRTL_FILE)
#########################################################################################
# create verilog files rules and variables
#########################################################################################
CIRCT_TARGETS = $(VSRC_SMEMS_FILE) $(VSRC_MODH_JSON)
CIRCT_TARGETS = $(VSRC_SMEMS_CONF) $(VSRC_MODH_JSON)
# DOC include start: FirrtlCompiler
$(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
@@ -170,14 +170,17 @@ firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
--lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \
--repl-seq-mem \
--repl-seq-mem-circuit=$(MODEL) \
--repl-seq-mem-file=$(VSRC_SMEMS_FILE) \
--repl-seq-mem-file=$(VSRC_SMEMS_CONF) \
--split-verilog \
-o $(VSRC_DUMP) \
$(FIRRTL_FILE)
# touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
>>>>>>> 9306c549 (Initial CIRCT integration [ci skip])
# DOC include end: FirrtlCompiler
$(TOP_MODS_FILE) $(HARNESS_MODS_FILE): $(VSRC_MODH_JSON)
$(base_dir)/scripts/dump-mods.py $(TOP) $^ > $(TOP_MODS_FILE)
$(base_dir)/scripts/dump-mods.py $(MODEL) $^ > $(HARNESS_MODS_FILE)
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
MACROCOMPILER_MODE ?= --mode synflops
$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TOP_SMEMS_CONF)
@@ -190,7 +193,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR) &: $(HARNESS_SMEMS_CONF) | $(TOP_SMEM
########################################################################################
# remove duplicate files and headers in list of simulation file inputs
########################################################################################
$(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes)
$(sim_common_files): $(sim_files)
sort -u $^ | grep -v '.*\.\(svh\|h\)$$' > $@
#########################################################################################

18
scripts/dump-mods.py Executable file
View File

@@ -0,0 +1,18 @@
#!/usr/bin/python
# dump all modules (deduped) given a specific module
#
# args
# $1 - module to dump all modules underneath (inclusive)
# $2 - module heirarchy file
import sys
import json
mod_name = sys.argv[1]
mod_file = sys.argv[2]
# open file
with open(mod_file, 'r') as modFile:
#print(json.load(modFile))

2
tools/barstools

Submodule tools/barstools updated: 064c8be7bb...be5ad1836a

19
variables.mk
View File

@@ -147,22 +147,15 @@ FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
VSRC_DUMP ?= $(build_dir)/vsrc
VSRC_SMEMS_FILE ?= $(VSRC_DUMP)/$(long_name).mems.v
VSRC_SMEMS_CONF ?= $(VSRC_DUMP)/$(long_name).mems.conf
VSRC_MODH_JSON ?= $(VSRC_DUMP)/mod-he.json
TOP_FILE ?= $(build_dir)/$(long_name).top.v
TOP_FIR ?= $(build_dir)/$(long_name).top.fir
TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json
TOP_SMEMS_FILE ?= $(build_dir)/$(long_name).top.mems.v
TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf
TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir
VSRC_SMEMS_FILE ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).mems.v
VSRC_SMEMS_FIR ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).mems.fir
HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v
HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir
HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json
HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v
HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf
HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir
# top only modules
TOP_MODS_FILE ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).top.f
HARNESS_MODS_FILE ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).top.f
BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img
BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))