E2E RocketConfig compile in Verilator
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20
variables.mk
20
variables.mk
@@ -146,16 +146,22 @@ endif
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FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
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ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
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VSRC_DUMP ?= $(build_dir)/vsrc
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INT_FIR ?= $(build_dir)/$(long_name).intermediate.fir
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INT_ANNO ?= $(build_dir)/$(long_name).intermediate.anno.json
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VSRC_DUMP ?= $(build_dir)
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VSRC_SMEMS_CONF ?= $(VSRC_DUMP)/$(long_name).mems.conf
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VSRC_MODH_JSON ?= $(VSRC_DUMP)/mod-he.json
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VSRC_SMEMS_FILE ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).mems.v
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VSRC_SMEMS_FIR ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).mems.fir
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VSRC_FILELIST ?= $(VSRC_DUMP)/filelist.f
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VSRC_BB_F ?= $(VSRC_DUMP)/firrtl_black_box_resource_files.json
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VSRC_SMEMS_FILE ?= $(VSRC_DUMP)/$(long_name).mems.v
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VSRC_SMEMS_FIR ?= $(VSRC_DUMP)/$(long_name).mems.fir
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# top only modules
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TOP_MODS_FILE ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).top.f
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HARNESS_MODS_FILE ?= $(build_dir)/$(VSRC_DUMP)/$(long_name).top.f
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TOP_MODS_FILE ?= $(VSRC_DUMP)/$(long_name).top.f
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ALL_MODS_FILE ?= $(VSRC_DUMP)/$(long_name).all.f
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BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img
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BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
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@@ -163,8 +169,6 @@ BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
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# files that contain lists of files needed for VCS or Verilator simulation
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SIM_FILE_REQS =
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sim_files ?= $(build_dir)/sim_files.f
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sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
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sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
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# single file that contains all files needed for VCS or Verilator simulation (unique and without .h's)
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sim_common_files ?= $(build_dir)/sim_files.common.f
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@@ -199,7 +203,7 @@ define run_scala_main
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cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)"
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endef
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FIRRTL_LOGLEVEL ?= error
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FIRRTL_LOGLEVEL ?= debug
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#########################################################################################
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# output directory for tests
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