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Merge pull request #1224 from ucb-bar/constellation-integrate

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Add support for NoC based interconnect with Constellation
This commit is contained in:
Jerry Zhao
2022-09-28 11:05:08 -07:00
committed by GitHub
parent 018aa7e1f0 07cad27315
commit b192a12040
28 changed files with 1016 additions and 33 deletions
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5
.github/scripts/defaults.sh vendored
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@@ -28,8 +28,9 @@ declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
grouping["group-accels"]="chipyard-fftgenerator chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-other"]="icenet testchipip"
grouping["group-other"]="icenet testchipip constellation"
grouping["group-fpga"]="arty vcu118"
# key value store to get the build strings
@@ -58,7 +59,9 @@ mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
mapping["chipyard-fftgenerator"]=" CONFIG=FFTRocketConfig"
mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
mapping["constellation"]=" SUB_PROJECT=constellation"
mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"
mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"

7
.github/scripts/remote-do-rtl-build.sh vendored
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@@ -18,6 +18,13 @@ cd $REMOTE_CHIPYARD_DIR
./scripts/init-submodules-no-riscv-tools.sh --force
./scripts/init-fpga.sh
# Constellation can run without espresso, but this improves
# elaboration time drastically
pushd $REMOTE_CHIPYARD_DIR/generators/constellation
scripts/install-espresso.sh $RISCV
popd
if [ $1 = "group-accels" ]; then
pushd $REMOTE_CHIPYARD_DIR/generators/gemmini/software
git submodule update --init --recursive gemmini-rocc-tests

6
.github/scripts/run-tests.sh vendored
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@@ -102,12 +102,18 @@ case $1 in
make -C $LOCAL_CHIPYARD_DIR/tests
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv run-binary-fast
;;
chipyard-constellation)
run_bmark ${mapping[$1]}
;;
icenet)
make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}
;;
testchipip)
make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}
;;
constellation)
make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}
;;
*)
echo "No set of tests for $1. Did you spell it right?"
exit 1

106
.github/workflows/chipyard-run-tests.yml vendored
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@@ -261,6 +261,28 @@ jobs:
with:
group-key: "group-cores"
prepare-chipyard-constellation:
name: prepare-chipyard-constellation
needs: setup-complete
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Build RTL on self-hosted
uses: ./.github/actions/prepare-rtl
with:
group-key: "group-constellation"
prepare-chipyard-peripherals:
name: prepare-chipyard-peripherals
needs: setup-complete
@@ -861,6 +883,53 @@ jobs:
group-key: "group-other"
project-key: "testchipip"
constellation-run-tests:
name: constellation-run-tests
needs: prepare-chipyard-other
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-other"
project-key: "constellation"
chipyard-constellation-run-tests:
name: chipyard-constellation-run-tests
needs: prepare-chipyard-constellation
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-constellation"
project-key: "chipyard-constellation"
firesim-run-tests:
name: firesim-run-tests
needs: setup-complete
@@ -939,16 +1008,35 @@ jobs:
# When adding new top level jobs, please add them to `needs` below
all_tests_passed:
name: "all tests passed"
needs: [commit-on-master-check, tutorial-setup-check, documentation-check,
chipyard-rocket-run-tests, chipyard-hetero-run-tests, chipyard-boom-run-tests, chipyard-cva6-run-tests, chipyard-ibex-run-tests,
chipyard-sodor-run-tests, chipyard-dmirocket-run-tests, chipyard-spiflashwrite-run-tests, chipyard-fftgenerator-run-tests,
chipyard-spiflashread-run-tests, chipyard-lbwif-run-tests, chipyard-sha3-run-tests,
chipyard-streaming-fir-run-tests, chipyard-streaming-passthrough-run-tests, chipyard-hwacha-run-tests,
chipyard-gemmini-run-tests, chipyard-nvdla-run-tests,
tracegen-boom-run-tests, tracegen-run-tests,
icenet-run-tests, testchipip-run-tests,
needs: [commit-on-master-check,
tutorial-setup-check,
documentation-check,
chipyard-rocket-run-tests,
chipyard-hetero-run-tests,
chipyard-boom-run-tests,
chipyard-cva6-run-tests,
chipyard-ibex-run-tests,
chipyard-sodor-run-tests,
chipyard-dmirocket-run-tests,
chipyard-spiflashwrite-run-tests,
chipyard-fftgenerator-run-tests,
chipyard-spiflashread-run-tests,
chipyard-lbwif-run-tests,
chipyard-sha3-run-tests,
chipyard-streaming-fir-run-tests,
chipyard-streaming-passthrough-run-tests,
chipyard-hwacha-run-tests,
chipyard-gemmini-run-tests,
chipyard-nvdla-run-tests,
chipyard-constellation-run-tests,
tracegen-boom-run-tests,
tracegen-run-tests,
icenet-run-tests,
testchipip-run-tests,
constellation-run-tests,
prepare-chipyard-fpga, # firesim-run-tests,
fireboom-run-tests, firesim-multiclock-run-tests]
fireboom-run-tests,
firesim-multiclock-run-tests]
runs-on: ubuntu-latest
steps:
- run: echo Success!

1
.gitignore vendored
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@@ -21,3 +21,4 @@ env-riscv-tools.sh
env-esp-tools.sh
.bsp/
.conda-env/
.#*

3
.gitmodules vendored
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@@ -127,3 +127,6 @@
[submodule "toolchains/libgloss"]
path = toolchains/libgloss
url = https://github.com/ucb-bar/libgloss-htif.git
[submodule "generators/constellation"]
path = generators/constellation
url = https://github.com/ucb-bar/constellation.git

8
build.sbt
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@@ -148,7 +148,13 @@ lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator)
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
constellation)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val constellation = (project in file("generators/constellation"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

2
docs/Advanced-Concepts/Top-Testharness.rst
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@@ -38,7 +38,7 @@ We also see this class define several ``ElaborationArtefacts``, files emitted af
Subsystem
^^^^^^^^^^^^^^^^^^^^^^^^^
Looking in `generators/chipyard/src/main/scala/Subsystem.scala <https://github.com/ucb-bar/chipyard/blob/master/generators/chipyard/src/main/scala/Subsystem.scala>`__, we can see how Chipyard's ``Subsystem``
Looking in `generators/chipyard/src/main/scala/Subsystem.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/Subsystem.scala>`__, we can see how Chipyard's ``Subsystem``
extends the ``BaseSubsystem`` abstract class. ``Subsystem`` mixes in the ``HasBoomAndRocketTiles`` trait that
defines and instantiates BOOM or Rocket tiles, depending on the parameters specified.
We also connect some basic IOs for each tile here, specifically the hartids and the reset vector.

3
docs/Chipyard-Basics/Chipyard-Components.rst
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@@ -47,6 +47,9 @@ Accelerators
System Components:
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
**constellation**
A generator for network-on-chip (NoC) interconnects.
**icenet**
A Network Interface Controller (NIC) designed to achieve up to 200 Gbps.

34
docs/Customization/NoC-SoCs.rst Normal file
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@@ -0,0 +1,34 @@
SoCs with NoC-based Interconnects
==================================
The primary way to integrate a network-on-chip into a Chipyard SoC is to map one of the standard TileLink crossbar-based buses (System Bus, Memory Bus, Control Bus, etc.) to a Constellation-generated NoC.
The interconnect can be mapped as a "private" interconnect for the TileLink bus, in which case a dedicated interconnect to carry the bus traffic will be generated.
Alternatively, the interconnect can be mapped to a shared global interconnect, in which case multiple TileLink buses can be transported over a single shared interconnect.
Private Interconnects
---------------------
An example of integrating dedicated private interconnects for the System Bus, Memory Bus, and Control Bus can be seen in the ``MultiNoCConfig`` of `generators/chipyard/src/main/scala/config/NoCConfigs.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/config/NoCConfigs.scala>`__.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/NoCConfigs.scala
:language: scala
:start-after: DOC include start: MultiNoCConfig
:end-before: DOC include end: MultiNoCConfig
Note that for each bus (``Sbus`` / ``Mbus`` / ``Cbus``), the configuration fragment provides both a parameterization of the private NoC, as well as a mapping between TileLink agents and physical NoC nodes.
For more information on how to construct the NoC parameters, see the `Constellation documentation <http://constellation.readthedocs.io>`__.
Shared Global Interconnect
---------------------------
An example of integrating a single global interconnect that supports transporting multiple TileLink buses can be seen in the ``SharedNoCConfig`` of `generators/chipyard/src/main/scala/config/NoCConfigs.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/config/NoCConfigs.scala>`__.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/NoCConfigs.scala
:language: scala
:start-after: DOC include start: SharedNoCConfig
:end-before: DOC include end: SharedNoCConfig
Note that for each bus, the configuration fragment provides only the mapping between TileLink agents and physical NoC nodes, while a separate fragement provides the configuration for the global interconnect.
For more information on how to construct the NoC parameters, see the `Constellation documentation <http://constellation.readthedocs.io>`__.

5
docs/Customization/index.rst
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@@ -3,7 +3,9 @@ Customization
These guides will walk you through customization of your system-on-chip:
- Contructing heterogenous systems-on-chip using the existing Chipyard generators and configuration system.
- Constructing heterogenous systems-on-chip using the existing Chipyard generators and configuration system.
- Constructing SoCs with a NoC (network-on-chip) based interconnect using Constellation
- How to include your custom Chisel sources in the Chipyard build system
@@ -36,6 +38,7 @@ We recommend reading all these pages in order. Hit next to get started!
:caption: Customization:
Heterogeneous-SoCs
NoC-SoCs
Custom-Chisel
Custom-Core
RoCC-or-MMIO

17
docs/Generators/Constellation.rst Normal file
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@@ -0,0 +1,17 @@
Constellation
========================
.. image:: ../_static/images/bigsoc.svg
`Constellation <https://github.com/ucb-bar/constellation>`__ is a Chisel NoC RTL generator framework designed from the ground up to support integration in a heterogeneous SoC and evaluation of highly irregular NoC architectures.
- Constellation generates **packet-switched wormhole-routed networks with virtual networks and credit-based flow control**
- Constellation supports **arbitrary directed graph network topologies**, including **irregular** and **hierarchical** network topologies
- Constellation includes a **routing algorithm verifier and routing-table compiler**, which can verify and generate deadlock-free routing tables for arbitrary topologies
- Constellation is a **protocol-independent transport layer**, yet is capable of compliant deadlock-free transport of protocols like **AXI-4** and **TileLink**
- Constellation supports drop-in **integration in Chipyard/Rocketchip SoCs**
- Constellation is **rigorously tested**, with almost 100 different tests across as many network configurations
Constellation is fully integrated into Chipyard, and can be used to generate almost any interconnect in a Chipyard/Rocketchip-based SoC.
For documentation on Constellation, see its `documentation pages <http://constellation.readthedocs.io>`__.

1
docs/Generators/index.rst
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@@ -21,6 +21,7 @@ so changes to the generators themselves will automatically be used when building
Rocket-Chip
Rocket
BOOM
Constellation
Hwacha
Gemmini
IceNet

558
docs/_static/images/bigsoc.svg vendored Normal file
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@@ -0,0 +1,558 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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1
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -33,6 +33,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution
with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
{
override lazy val module = new DigitalTopModule(this)
}

188
generators/chipyard/src/main/scala/config/NoCConfigs.scala Normal file
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@@ -0,0 +1,188 @@
package chipyard
import freechips.rocketchip.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{SBUS, MBUS}
import constellation.channel._
import constellation.routing._
import constellation.topology._
import constellation.noc._
import constellation.soc.{GlobalNoCParams}
import scala.collection.immutable.ListMap
/*
* This config demonstrates a SoC architecture with three different
* independent interconnects. The SBus interconnect is the main
* backbone, handling core traffic to the L2s and peripherals.
* The MBus handles requests to the DRAM and external memory.
* The CBus handles requests to control devices.
*
* Topologies:
*
* 12 - 13 - 14 - 15
* | | | |
* 8 -- 9 - 10 - 11 0 -- 1 -- 2 -- 3
* | | | | | |
* 4 -- 5 -- 6 -- 7 7 -- 6 -- 5 -- 4
* | | | |
* 0 -- 1 -- 2 -- 3
*
* This table describes the mappings of each edge onto the network
*
* SI/SO: Inward/outward names into sbus
* MI/MO: Inward/outward names into mbus
*
* |(12)__________|(13)__________|(14)__________|(15)__________|
* | | Core 6 | Core 7 | |
* | | SI:Core 6 | SI:Core 7 | |
* |(8)___________|(9)___________|(10)__________|(11)__________|
* | Core 4 | L2 2 | L2 3 | Core 5 |
* | SI:Core 4 | S0:system[2] | SO:system[3] | SI:Core 5 |
* |(4)___________|(5)___________|(6)___________|(7)___________|
* | Core 2 | L2 0 | L2 1 | Core 3 |
* | SI:Core 2 | SO:system[0] | SO:system[1] | SI:Core 3 |
* |(0)___________|(1)___________|(2)___________|(3)___________|
* | FBus | Core 0 | Core 1 | Pbus |
* | SI:serial-tl | SI:Core 0 | SI:Core 1 | SO:pbus |
* |______________|______________|______________|______________|
*
* |(0)___________|(1)___________|(2)___________|(3)___________|
* | DRAM 0 | L2 0 | L2 1 | DRAM 1 |
* | M0:system[0] | MI:L2[0] | MI:L2[1] | M0:system[1] |
* | M0:serdesser | | | |
* |______________|______________|______________|______________|
* |||||||||||||| ||||||||||||||
* |(7)___________|(6)___________|(5)___________|(4)___________|
* | DRAM 2 | L2 2 | L2 3 | DRAM 3 |
* | M0:system[2] | MI:L2[2] | MI:L2[3] | M0:system[3] |
* | | | | |
* |______________|______________|______________|______________|
*/
// DOC include start: MultiNoCConfig
class MultiNoCConfig extends Config(
new constellation.soc.WithCbusNoC(constellation.protocol.TLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"serial-tl" -> 0),
outNodeMapping = ListMap(
"error" -> 1, "l2[0]" -> 2, "pbus" -> 3, "plic" -> 4,
"clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "tileClockGater" -> 8, "tileResetSetter" -> 9)),
NoCParams(
topology = TerminalRouter(BidirectionalLine(10)),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }),
routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1))
)) ++
new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"L2 InclusiveCache[0]" -> 1, "L2 InclusiveCache[1]" -> 2,
"L2 InclusiveCache[2]" -> 5, "L2 InclusiveCache[3]" -> 6),
outNodeMapping = ListMap(
"system[0]" -> 0, "system[1]" -> 3, "system[2]" -> 4 , "system[3]" -> 7,
"serdesser" -> 0)),
NoCParams(
topology = TerminalRouter(BidirectionalTorus1D(8)),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalTorus1DShortestRouting()), 5, 2))
)) ++
new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Core 0" -> 1, "Core 1" -> 2, "Core 2" -> 4 , "Core 3" -> 7,
"Core 4" -> 8, "Core 5" -> 11, "Core 6" -> 13, "Core 7" -> 14,
"serial-tl" -> 0),
outNodeMapping = ListMap(
"system[0]" -> 5, "system[1]" -> 6, "system[2]" -> 9, "system[3]" -> 10,
"pbus" -> 3)),
NoCParams(
topology = TerminalRouter(Mesh2D(4, 4)),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }),
routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1))
)) ++
new freechips.rocketchip.subsystem.WithNBigCores(8) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
new chipyard.config.AbstractConfig
)
// DOC include end: MultiNoCConfig
/*
* 10 - 11 - 12 - 13 - 14
* |
* 0 --- 1 --- 2 --- 3
* | |
* 9 4
* | |
* 8 --- 7 --- 6 --- 5
* |
* 15 - 16 - 17 - 18 - 19
*
* SI/SO: Inward/outward names into sbus
* MI/MO: Inward/outward names into mbus
*
* Agent | Bus | String | node
* ================================
* Core 0 | SI | Core 0 | 2
* Core 1 | SI | Core 1 | 10
* Core 2 | SI | Core 2 | 11
* Core 3 | SI | Core 3 | 13
* Core 4 | SI | Core 4 | 14
* Core 5 | SI | Core 5 | 15
* Core 6 | SI | Core 6 | 16
* Core 7 | SI | Core 7 | 18
* Core 8 | SI | Core 8 | 19
* fbus | SI | serial-tl | 9
* pbus | SO | pbus | 4
* L2 0 | SO | system[0] | 0
* L2 1 | SO | system[1] | 2
* L2 2 | SO | system[2] | 8
* L2 3 | SO | system[3] | 6
* L2 0 | MI | Cache[0] | 0
* L2 1 | MI | Cache[1] | 2
* L2 2 | MI | Cache[2] | 8
* L2 3 | MI | Cache[3] | 6
* DRAM 0 | MO | system[0] | 3
* DRAM 1 | MO | system[1] | 5
* extram | MO | serdesser | 9
*/
// DOC include start: SharedNoCConfig
class SharedNoCConfig extends Config(
new constellation.soc.WithGlobalNoC(GlobalNoCParams(
NoCParams(
topology = TerminalRouter(HierarchicalTopology(
base = UnidirectionalTorus1D(10),
children = Seq(HierarchicalSubTopology(1, 2, BidirectionalLine(5)),
HierarchicalSubTopology(7, 2, BidirectionalLine(5))))),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(22) { UserVirtualChannelParams(4) }),
routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(HierarchicalRouting(
baseRouting = UnidirectionalTorus1DDatelineRouting(),
childRouting = Seq(BidirectionalLineRouting(),
BidirectionalLineRouting()))), 10, 2)
)
)) ++
new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6),
outNodeMapping = ListMap(
"system[0]" -> 3, "system[1]" -> 5,
"serdesser" -> 9))
), true) ++
new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"serial-tl" -> 9, "Core 0" -> 2,
"Core 1" -> 10, "Core 2" -> 11, "Core 3" -> 13, "Core 4" -> 14,
"Core 5" -> 15, "Core 6" -> 16, "Core 7" -> 18, "Core 8" -> 19),
outNodeMapping = ListMap(
"system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6,
"pbus" -> 4))
), true) ++
new freechips.rocketchip.subsystem.WithNBigCores(8) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
new chipyard.config.AbstractConfig
)
// DOC include end: SharedNoCConfig

2
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -23,7 +23,7 @@ class TinyRocketConfig extends Config(
// DOC include start: FFTRocketConfig
class FFTRocketConfig extends Config(
new fftgenerator.WithFFTGenerator(baseAddr=0x2000, numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at 0x2000 with 16bit fixed-point numbers.
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at 0x2000 with 16bit fixed-point numbers.
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: FFTRocketConfig

48
generators/chipyard/src/main/scala/config/TutorialConfigs.scala
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@@ -1,6 +1,12 @@
package chipyard
import freechips.rocketchip.config.{Config}
import constellation.channel._
import constellation.routing._
import constellation.topology._
import constellation.noc._
import constellation.soc.{GlobalNoCParams}
import scala.collection.immutable.ListMap
// This file is designed to accompany a live tutorial, with slides.
// For each of 4 phases, participants will customize and build a
@@ -68,3 +74,45 @@ class TutorialSha3BlackBoxConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig
)
// Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators
class TutorialNoCConfig extends Config(
// Try changing the dimensions of the Mesh topology
new constellation.soc.WithGlobalNoC(constellation.soc.GlobalNoCParams(
NoCParams(
topology = TerminalRouter(Mesh2D(3, 4)),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(12) { UserVirtualChannelParams(4) }),
routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(
Mesh2DEscapeRouting()), 10, 1)
)
)) ++
// The inNodeMapping and outNodeMapping values are the physical identifiers of
// routers on the topology to map the agents to. Try changing these to any
// value within the range [0, topology.nNodes)
new constellation.soc.WithPbusNoC(constellation.protocol.TLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap("Core" -> 7),
outNodeMapping = ListMap(
"pbus" -> 8, "uart" -> 9, "control" -> 10, "gcd" -> 11,
"writeQueue[0]" -> 0, "writeQueue[1]" -> 1, "tailChain[0]" -> 2))
), true) ++
new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
constellation.protocol.DiplomaticNetworkNodeMapping(
inNodeMapping = ListMap(
"Core 0" -> 0, "Core 1" -> 1,
"serial-tl" -> 2),
outNodeMapping = ListMap(
"system[0]" -> 3, "system[1]" -> 4, "system[2]" -> 5, "system[3]" -> 6,
"pbus" -> 7))
), true) ++
new chipyard.example.WithGCD ++
new chipyard.harness.WithLoopbackNIC ++
new icenet.WithIceNIC ++
new fftgenerator.WithFFTGenerator(numPoints=8) ++
new chipyard.example.WithStreamingFIR ++
new chipyard.example.WithStreamingPassthrough ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new freechips.rocketchip.subsystem.WithNBigCores(2) ++
new chipyard.config.AbstractConfig
)

4
generators/chipyard/src/main/scala/example/GCD.scala
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@@ -13,7 +13,7 @@ import freechips.rocketchip.util.UIntIsOneOf
// DOC include start: GCD params
case class GCDParams(
address: BigInt = 0x2000,
address: BigInt = 0x1000,
width: Int = 32,
useAXI4: Boolean = false,
useBlackBox: Boolean = true)
@@ -201,7 +201,7 @@ trait CanHavePeripheryGCDModuleImp extends LazyModuleImp {
// DOC include start: GCD config fragment
class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => {
class WithGCD(useAXI4: Boolean = false, useBlackBox: Boolean = false) extends Config((site, here, up) => {
case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox))
})
// DOC include end: GCD config fragment

4
generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
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@@ -16,8 +16,8 @@ import freechips.rocketchip.subsystem._
// Simple passthrough to use as testbed sanity check
// StreamingPassthrough params
case class StreamingPassthroughParams(
writeAddress: BigInt = 0x2000,
readAddress: BigInt = 0x2100,
writeAddress: BigInt = 0x2200,
readAddress: BigInt = 0x2300,
depth: Int
)

1
generators/constellation Submodule

Submodule generators/constellation added at b93fde3e28

2
generators/fft-generator

Submodule generators/fft-generator updated: 4c335ff6ab...40357f00a8

5
scripts/tutorial-patches/build.sbt.patch
View File

@@ -2,14 +2,15 @@ diff --git a/build.sbt b/build.sbt
index bbbb8251..b7adcb73 100644
--- a/build.sbt
+++ b/build.sbt
@@ -143,7 +143,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
@@ -143,8 +143,8 @@ lazy val testchipip = (project in file("generators/testchipip"))
lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
+// sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator)
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
constellation)
.settings(libraryDependencies ++= rocketLibDeps.value)
@@ -189,11 +189,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
.settings(libraryDependencies ++= rocketLibDeps.value)

2
tests/Makefile
View File

@@ -6,7 +6,7 @@ LDFLAGS= -static
include libgloss.mk
PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \
streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft
streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd
spiflash.img: spiflash.py
python3 $<

6
tests/fft.c
View File

@@ -4,8 +4,8 @@
#include <inttypes.h>
#include <math.h>
#define FFT_WRITE_LANE 0x2000
#define FFT_RD_LANE_BASE 0x2008
#define FFT_WRITE_LANE 0x2400
#define FFT_RD_LANE_BASE 0x2408
// addr of read lane i is FFT_RD_LANE_BASE + i * 8
// from generators/fft-generator/test_pts.py (in the fft-generator repo)
@@ -68,4 +68,4 @@ int main(void) {
printf("PASS: FFT Test Passed\n");
return 0;
}
}

9
tests/gcd.c
View File

@@ -1,9 +1,9 @@
#include "mmio.h"
#define GCD_STATUS 0x2000
#define GCD_X 0x2004
#define GCD_Y 0x2008
#define GCD_GCD 0x200C
#define GCD_STATUS 0x1000
#define GCD_X 0x1004
#define GCD_Y 0x1008
#define GCD_GCD 0x100C
unsigned int gcd_ref(unsigned int x, unsigned int y) {
while (y != 0) {
@@ -37,6 +37,7 @@ int main(void)
printf("Hardware result %d does not match reference value %d\n", result, ref);
return 1;
}
printf("Hardware result %d is correct for GCD\n", result);
return 0;
}
// DOC include end: GCD test

8
tests/streaming-passthrough.c
View File

@@ -1,7 +1,7 @@
#define PASSTHROUGH_WRITE 0x2000
#define PASSTHROUGH_WRITE_COUNT 0x2008
#define PASSTHROUGH_READ 0x2100
#define PASSTHROUGH_READ_COUNT 0x2108
#define PASSTHROUGH_WRITE 0x2200
#define PASSTHROUGH_WRITE_COUNT 0x2208
#define PASSTHROUGH_READ 0x2300
#define PASSTHROUGH_READ_COUNT 0x2308
#include "mmio.h"

13
variables.mk
View File

@@ -111,6 +111,19 @@ ifeq ($(SUB_PROJECT),icenet)
TB ?= TestDriver
TOP ?= UnitTestSuite
endif
# For Constellation developers
ifeq ($(SUB_PROJECT),constellation)
SBT_PROJECT ?= chipyard
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
MODEL_PACKAGE ?= constellation.test
CONFIG ?= TestConfig00
CONFIG_PACKAGE ?= constellation.test
GENERATOR_PACKAGE ?= chipyard
TB ?= TestDriver
TOP ?= NoC
endif
#########################################################################################
# path to rocket-chip and testchipip