Merge pull request #1884 from ucb-bar/gcd_io

Add GCD IOBinders examples

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -59,6 +59,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithNICIOPunchthrough ++
   new chipyard.iobinders.WithTraceIOPunchthrough ++
   new chipyard.iobinders.WithUARTTSIPunchthrough ++
+  new chipyard.iobinders.WithGCDBusyPunchthrough ++
   new chipyard.iobinders.WithNMITiedOff ++
 
 

generators/chipyard/src/main/scala/iobinders/IOBinders.scala

@@ -39,6 +39,7 @@ import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
 import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
+import chipyard.example.{CanHavePeripheryGCD}
 
 import scala.reflect.{ClassTag}
 
@@ -540,3 +541,11 @@ class WithNMITiedOff extends ComposeIOBinder({
     (Nil, Nil)
   }
 })
+
+class WithGCDBusyPunchthrough extends OverrideIOBinder({
+  (system: CanHavePeripheryGCD) => system.gcd_busy.map { busy =>
+    val io_gcd_busy = IO(Output(Bool()))
+    io_gcd_busy := busy
+    (Seq(GCDBusyPort(() => io_gcd_busy)), Nil)
+  }.getOrElse((Nil, Nil))
+})

generators/chipyard/src/main/scala/iobinders/Ports.scala

@@ -109,3 +109,5 @@ case class JTAGResetPort   (val getIO: () => Reset)
 case class TLMemPort       (val getIO: () => HeterogeneousBag[TLBundle])
     extends Port[HeterogeneousBag[TLBundle]]
 
+case class GCDBusyPort     (val getIO: () => Bool)
+    extends Port[Bool]