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Fix remaining HarnessBinders bugs

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This commit is contained in:
Jerry Zhao
2020-09-04 20:03:12 -07:00
parent 0f50e4d118
commit b613c14f1c
3 changed files with 14 additions and 11 deletions
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4
.circleci/defaults.sh
View File

@@ -61,8 +61,8 @@ mapping["chipyard-ariane"]=" CONFIG=ArianeConfig"
mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem"
mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig TOP=TraceGenSystem"
mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"
mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"

5
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -240,7 +240,10 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
class WithTiedOffSerial extends OverrideHarnessBinder({
(system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
ports.map { case p: SerialIO => SerialAdapter.tieoff(Some(p)) }
ports.map {
case p: SerialIO => SerialAdapter.tieoff(Some(p))
case _ =>
}
Nil
}
})

16
generators/chipyard/src/main/scala/IOBinders.scala
View File

@@ -270,8 +270,8 @@ class WithAXI4MemPunchthrough extends OverrideIOBinder({
} else {
None
}
val ports = system.mem_axi4.map({ m =>
val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_mem")
val ports = system.mem_axi4.zipWithIndex.map({ case (m, i) =>
val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName(s"axi4_mem_${i}")
p <> m
p
})
@@ -286,8 +286,8 @@ class WithAXI4MMIOPunchthrough extends OverrideIOBinder({
} else {
None
}
val ports = system.mmio_axi4.map({ m =>
val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_mmio")
val ports = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName(s"axi4_mmio_${i}")
p <> m
p
})
@@ -297,11 +297,11 @@ class WithAXI4MMIOPunchthrough extends OverrideIOBinder({
class WithL2FBusAXI4Punchthrough extends OverrideIOBinder({
(system: CanHaveSlaveAXI4Port) => {
val port = system.l2_frontend_bus_axi4.map { m =>
val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName("axi4_fbus")
p <> m
val port = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>
val p = IO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_fbus_${i}")
m <> p
p
}
})
(port, Nil)
}
})