Add option to add async queues between chip-serialIO and harness serdes
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@@ -238,23 +238,35 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
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})
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class WithSerialAdapterTiedOff extends OverrideHarnessBinder({
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class WithSerialAdapterTiedOff(asyncQueue: Boolean = false) extends OverrideHarnessBinder({
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(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
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implicit val p = chipyard.iobinders.GetSystemParameters(system)
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ports.map({ port =>
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val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
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val bits = if (asyncQueue) {
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SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
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} else {
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port.bits
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}
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val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
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SerialAdapter.tieoff(ram.module.io.tsi_ser)
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})
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}
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})
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class WithSimSerial extends OverrideHarnessBinder({
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class WithSimSerial(asyncQueue: Boolean = false) extends OverrideHarnessBinder({
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(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
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implicit val p = chipyard.iobinders.GetSystemParameters(system)
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ports.map({ port =>
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val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
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val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, port.clock, th.harnessReset.asBool)
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when (success) { th.success := true.B }
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val bits = if (asyncQueue) {
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SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
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} else {
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port.bits
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}
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withClockAndReset(th.harnessClock, th.harnessReset) {
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val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
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val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.harnessClock, th.harnessReset.asBool)
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when (success) { th.success := true.B }
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}
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})
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}
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})
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Submodule generators/testchipip updated: 282ca2e25e...6e2db28a16
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